TLC320AD57 Datasheet, PDF (13/21 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

available as a master are 16-bit modes. Two of the modes differ as MSB first versus LSB first. These two
modes set SCLK = LRClk × 32. This is one half the frequency used in the other transfer modes [see Figures
2–3(d) and 2–3(e)]. The third 16-bit mode provides the data MSB first with one clock delay after LRClk [see
Figure 2–3(a)].
Mode 011
SCLK
Fsync
DOUT
LRClk
(a) MASTER MODE (Fsync bound)
15 14 ^{. . .} 1 0
15 14 ^{. . .} 1 0
64 SCLKs
Left
Right
Mode 100
SCLK
Fsync
(b) 18-BIT MASTER MODE
DOUT
17 16 ^{. . .} 1 0
17 16 ^{. . .} 1 0
17
LRClk
Left
64 SCLKs
Right
Mode 101
SCLK
Fsync
DOUT
LRClk
Mode 110
SCLK
Fsync
DOUT
LRClk
(c) 18-BIT MASTER MODE
0 1 ^{. . .} 16 17
01
. . . _{16 17}
64 SCLKs
Left
Right
(d) DSP CONTINUOUS MODE
15
14
Left
...
1
0
15
14
32 SCLKs
Right
...
1
0
15
Mode 111
SCLK
Fsync
DOUT
LRClk
(e) DSP CONTINUOUS MODE
0
1
Left
...
14
15
0
1
32 SCLKs
Right
...
14
15
0
Figure 2–3. Serial Master Transfer Modes
2–5