TLC320AD57 Datasheet, PDF (10/21 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

2.1.2 Reset Function
The conversion process is not initiated until the first rising edges on both SCLK and LRClk are detected after
DigPD is pulled low. This synchronizes the conversion cycle. All conversions are performed at a fixed LRClk
rate [MCLK /256 (CMODE low) or MCLK /384 (CMODE high)] after the initial synchronization.
DigPD
tsu1
Slave Mode Digital Power Down
LRClk
DOUT
Data Valid
(a)
DigPD
LRClk
DOUT
tsu2
Master Mode Digital Power Down
Data Valid
(b)
td1
Analog Power Down
AnaPD
DOUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(c)
Figure 2–1. Power-Down Timing Relationships
2–2