TLC320AD57 Datasheet, PDF (7/21 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

1.5 Terminal Functions (Continued)
TERMINAL
I/O
NAME
NO.
DESCRIPTION
DVSS
DigPD
19
I Digital ground
10
I Digital power-down mode. The digital power-down mode shuts down the digital
filters and clock generators. All digital outputs are brought to unasserted levels.
When DigPD is pulled low, normal operation of the device resumes.
Fsync
17 I/O Frame synchronization. Fsync designates valid data from the ADC.
HPByp
7
I High-pass filter bypass. When HPByp is high, the high-pass filter is bypassed. This
allows dc analog signal conversion.
INLM
2
I Inverting input to left analog input amplifier
INLP
1
I Noninverting input to left analog input amplifier
INRM
27
I Inverting input to right analog input amplifier
INRP
28
I Noninverting input to right analog input amplifier
LGND
25
I Logic-power-supply ground for analog modulator
LRClk
14 I/O Left/right clock. LRClk signifies whether the serial data is associated with the left
channel ADC (when high) or the right channel ADC (when low). LRClk is low when
DigPD is high.
MCLK
20
I Master clock. MCLK derives all of the key logic signals of the sigma-delta audio
ADC. The nominal input frequency range is 18.432 MHz to 256 kHz.
MODE0–MODE2 8, 13, I Serial modes. MODE0–MODE2 configure this device for many different modes of
22
operation. The different configurations are:
Master versus slave
16 bit versus 18 bit
MSB first versus LSB first
Slave: Fsync controlled versus Fsync high
Each of these modes is described in the Serial Interface section with timing
diagrams.
MODE MASTER/
MSB/LSB
0 1 2 SLAVE
BITS
FIRST
0 0 0 slave
up to 18
MSB
0 0 1 slave
18
LSB
0 1 0 slave
up to 18
MSB
0 1 1 master
16
MSB
1 0 0 master
18
MSB
1 0 1 master
18
LSB
1 1 0 master
16
MSB
1 1 1 master
16
LSB
OSFL, OSFR
9, 21
O Over scale flag left/right. If the left /right channel analog input exceeds the full scale
input range for two consecutive conversions, OSFL and OSFR are set high for 4096
LRClk periods. OSFL and OSFR are low when DigPD is high.
SCLK
15 I/O Shift clock. If SCLK is confirgured as an input, SCLK clocks serial data out of the
sigma-delta audio ADC. If SCLK is configured as an output, SCLK stops clocking
when DigPD is high.
TEST
11
I Test mode. TEST should be low for normal operation.
REFI
3
I Input voltage for modulator reference (normally connected to REFO, terminal 26).
REFO
26
I Internal voltage reference
Vlogic
24
I Logic power supply (5 V) for analog modulator
1–3