TLC320AD57 Datasheet, PDF (6/21 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

1.3 Terminal Assignments
DW PACKAGE
(TOP VIEW)
INLP ₁
INLM 2
REFI 3
AV_DD 4
AV_SS 5
AnaPD 6
HPByp 7
MODE2 8
OSFL 9
DigPD ¹⁰
TEST ¹¹
CMODE ¹²
MODE0 ¹³
LRClk ¹⁴
28 ^INRP
27 INRM
26 REFO
25 LGND
24 Vlogic
23 NC
22 MODE1
21 OSFR
20 MCLK
19 _DVSS
18 _DVDD
17 _Fsync
16 _DOUT
15 _SCLK
NC – No internal connection
1.4 Ordering Information
TA
0°C to 70°C
PACKAGE
SMALL OUTLINE
(DW)
TLC320AD57CDW
1.5 Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
AnaPD
6
I Analog power-down mode. The analog power-down mode disables the analog
modulators. The single-bit modulator outputs become invalid, which renders the
outputs of the digital filters invalid. When AnaPD is pulled low, normal operation of the
device resumes.
AVDD
AVSS
CMODE
4
I Analog supply voltage
5
I Analog ground
12
I Clock mode. CMODE selects between two methods of determining the master clock
frequency. When CMODE is high, the master clock input is 384× the conversion
frequency. When CMODE is low, the master clock input is 256× the conversion
frequency.
DOUT
16 O Data output. DOUT transmits the sigma-delta audio analog-to-digital converter (ADC)
output data to a digital signal processor (DSP) serial port or other compatible serial
interface and is synchronized to SCLK. DOUT is low when DigPD is high.
DVDD
18
I Digital supply voltage
1–2