LP2996 Datasheet, PDF (9/21 Pages) National Semiconductor (TI) – DDR Termination Regulator

Pin Descriptions
AVIN AND PVIN
AVIN and PVIN are the input supply pins for the LP2996. AVIN
is used to supply all the internal control circuitry. PVIN, how-
ever, is used exclusively to provide the rail voltage for the
output stage used to create VTT. These pins have the capa-
bility to work off separate supplies depending on the applica-
tion. Higher voltages on PVIN will increase the maximum
continuous output current because of output RDSON limita-
tions at voltages close to VTT. The disadvantage of high
values of PVIN is that the internal power loss will also in-
crease, thermally limiting the design. For SSTL-2 applica-
tions, a good compromise would be to connect the AVIN and
PVIN directly together at 2.5V. This eliminates the need for
bypassing the two supply pins separately. The only limitation
on input voltage selection is that PVIN must be equal to or
lower than AVIN. It is recommended to connect PVIN to volt-
age rails equal to or less than 3.3V to prevent the thermal limit
from tripping because of excessive internal power dissipation.
If the junction temperature exceeds the thermal shutdown
than the part will enter a shutdown state identical to the man-
ual shutdown where V_TT is tri-stated and V_REF remains active.
VDDQ
VDDQ is the input used to create the internal reference volt-
age for regulating V_TT. The reference voltage is generated
from a resistor divider of two internal 50kΩ resistors. This
guarantees that V_TT will track VDDQ / 2 precisely. The optimal
implementation of VDDQ is as a remote sense. This can be
achieved by connecting VDDQ directly to the 2.5V rail at the
DIMM instead of AVIN and PVIN. This ensures that the ref-
erence voltage tracks the DDR memory rails precisely without
a large voltage drop from the power lines. For SSTL-2 appli-
cations VDDQ will be a 2.5V signal, which will create a 1.25V
termination voltage at V_TT (See Electrical Characteristics Ta-
ble for exact values of V_TT over temperature).
V_SENSE
The purpose of the sense pin is to provide improved remote
load regulation. In most motherboard applications the termi-
nation resistors will connect to V_TT in a long plane. If the output
voltage was regulated only at the output of the LP2996 then
the long trace will cause a significant IR drop resulting in a
termination voltage lower at one end of the bus than the other.
The V_SENSE pin can be used to improve this performance, by
connecting it to the middle of the bus. This will provide a better
distribution across the entire termination bus. If remote load
regulation is not used then the V_SENSE pin must still be con-
nected to V_TT. Care should be taken when a long V_SENSE trace
is implemented in close proximity to the memory. Noise pick-
up in the V_SENSE trace can cause problems with precise
regulation of V_TT. A small 0.1uF ceramic capacitor placed next
to the V_SENSE pin can help filter any high frequency signals
and preventing errors.
SHUTDOWN
The LP2996 contains an active low shutdown pin that can be
used to tri-state VTT. During shutdown V_TT should not be ex-
posed to voltages that exceed AVIN. With the shutdown pin
asserted low the quiescent current of the LP2996 will drop,
however, V_DDQ will always maintain its constant impedance
of 100kΩ for generating the internal reference. Therefore to
calculate the total power loss in shutdown both currents need
to be considered. For more information refer to the Thermal
Dissipation section. The shutdown pin also has an internal
pull-up current, therefore to turn the part on the shutdown pin
can either be connected to AVIN or left open.
V_REF
V_REF provides the buffered output of the internal reference
voltage VDDQ / 2. This output should be used to provide the
reference voltage for the Northbridge chipset and memory.
Since these inputs are typically an extremely high impedance,
there should be little current drawn from V_REF. For improved
performance, an output bypass capacitor can be used, locat-
ed close to the pin, to help with noise. A ceramic capacitor in
the range of 0.1 µF to 0.01 µF is recommended. This output
remains active during the shutdown state and thermal shut-
down events for the suspend to RAM functionality.
V_TT
V_TT is the regulated output that is used to terminate the bus
resistors. It is capable of sinking and sourcing current while
regulating the output precisely to VDDQ / 2. The LP2996 is
designed to handle peak transient currents of up to ± 3A with
a fast transient response. The maximum continuous current
is a function of V_IN and can be viewed in the TYPICAL PER-
FORMANCE CHARACTERISTICS section. If a transient is
expected to last above the maximum continuous current rat-
ing for a significant amount of time then the output capacitor
should be sized large enough to prevent an excessive voltage
drop. Despite the fact that the LP2996 is designed to handle
large transient output currents it is not capable of handling
these for long durations, under all conditions. The reason for
this is the standard packages are not able to thermally dissi-
pate the heat as a result of the internal power loss. If large
currents are required for longer durations, then care should
be taken to ensure that the maximum junction temperature is
not exceeded. Proper thermal derating should always be
used (please refer to the Thermal Dissipation section). If the
junction temperature exceeds the thermal shutdown point
than V_TT will tri-state until the part returns below the hysteretic
trip-point.
Component Selections
INPUT CAPACITOR
The LP2996 does not require a capacitor for input stability,
but it is recommended for improved performance during large
load transients to prevent the input rail from dropping. The
input capacitor should be located as close as possible to the
PVIN pin. Several recommendations exist dependent on the
application required. A typical value recommended for AL
electrolytic capacitors is 50 µF. Ceramic capacitors can also
be used, a value in the range of 10 µF with X5R or better would
be an ideal choice. The input capacitance can be reduced if
the LP2996 is placed close to the bulk capacitance from the
output of the 2.5V DC-DC converter. If the two supply rails
(AVIN and PVIN) are separated then the 47uF capacitor
should be placed as close to possible to the PVIN rail. An
additional 0.1uF ceramic capacitor can be placed on the AVIN
rail to prevent excessive noise from coupling into the device.
OUTPUT CAPACITOR
The LP2996 has been designed to be insensitive of output
capacitor size or ESR (Equivalent Series Resistance). This
allows the flexibility to use any capacitor desired. The choice
for output capacitor will be determined solely on the applica-
tion and the requirements for load transient response of V_TT.
As a general recommendation the output capacitor should be
sized above 100 µF with a low ESR for SSTL applications with
DDR-SDRAM. The value of ESR should be determined by the
9
www.ti.com