LP2996 Datasheet, PDF (8/21 Pages) National Semiconductor (TI) – DDR Termination Regulator

Description
The LP2996 is a linear bus termination regulator designed to
meet the JEDEC requirements of SSTL-2. The output, V_TT is
capable of sinking and sourcing current while regulating the
output voltage equal to VDDQ / 2. The output stage has been
designed to maintain excellent load regulation while prevent-
ing shoot through. The LP2996 also incorporates two distinct
power rails that separates the analog circuitry from the power
output stage. This allows a split rail approach to be utilized to
decrease internal power dissipation. It also permits the
LP2996 to provide a termination solution for the next gener-
ation of DDR-SDRAM memory (DDRII). For new designs, the
LP2997 or LP2998 is recommended for DDR-II applications.
The LP2996 can also be used to provide a termination voltage
for other logic schemes such as SSTL-3 or HSTL.
Series Stub Termination Logic (SSTL) was created to im-
prove signal integrity of the data transmission across the
memory bus. This termination scheme is essential to prevent
data error from signal reflections while transmitting at high
frequencies encountered with DDR-SDRAM. The most com-
mon form of termination is Class II single parallel termination.
This involves one R_S series resistor from the chipset to the
memory and one R_T termination resistor. Typical values for
R_S and R_T are 25 Ohms, although these can be changed to
scale the current requirements from the LP2996. This imple-
mentation can be seen below in Figure 1.
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FIGURE 1. SSTL-Termination Scheme
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