LP2996 Datasheet, PDF (14/21 Pages) National Semiconductor (TI) – DDR Termination Regulator

LEVEL SHIFTING
If standards other than SSTL-2 are required, such as SSTL-3,
it may be necessary to use a different scaling factor than 0.5
times V_DDQ for regulating the output voltage. Several options
are available to scale the output to any voltage required. One
method is to level shift the output by using feedback resistors
from V_TT to the V_SENSE pin. This has been illustrated in Figures
10 and 11. Figure 10 shows how to use two resistors to level
shift V_TT above the internal reference voltage of VDDQ/2. To
calculate the exact voltage at V_TT the following equation can
be used.
V_TT = VDDQ/2 ( 1 + R1/R2)
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FIGURE 10. Increasing VTT by Level Shifting
Conversely, the R2 resistor can be placed between V_SENSE
and V_DDQ to shift the V_TT output lower than the internal refer-
ence voltage of VDDQ/2. The equations relating VTT and the
resistors can be seen below:
V_TT = VDDQ/2 (1 - R1/R2)
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FIGURE 11. Decreasing VTT by Level Shifting
HSTL APPLICATIONS
The LP2996 can be easily adapted for HSTL applications by
connecting V_DDQ to the 1.5V rail. This will produce a V_TT and
V_REF voltage of approximately 0.75V for the termination re-
sistors. AVIN and PVIN should be connected to a 2.5V rail for
optimal performance.
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FIGURE 12. HSTL Application
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