DS99R103_13 Datasheet, PDF (9/29 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

www.ti.com
DS99R103, DS99R104
SNLS241D – MARCH 2007 – REVISED APRIL 2013
DIN
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
t_SD
TCLK
DOUT0-23
DCA, DCB
STOP START
STOP START
STOP START
STOP START
STOP
SYMBOL N-4 ^{BIT BIT} SYMBOL N-3 ^{BIT BIT} SYMBOL N-2 ^{BIT BIT} SYMBOL N-1 ^{BIT BIT} SYMBOL N ^BIT
012
23
012
23
012
23
012
23
012
23
Figure 8. Serializer Delay
Ideal Data Bit
Beginning
Ideal Data Bit
End
TxOUT_E_O
t_BIT(1/2UI)
t_BIT(1/2UI)
Ideal Center Position (t_BIT/2)
t_BIT (1UI)
Figure 9. Transmitter Output Eye Opening (TxOUT_E_O)
24
DIN
DOUT+
R_L
DOUT-
TCLK
VOD = (D_OUT+) – (D_{OUT -})
Differential output signal is shown as (D_OUT+) – (D_{OUT -}), device in Data Transfer mode.
Figure 10. Serializer VOD Diagram
Deserializer
8 pF
lumped
Single-ended
Signal
80%
20%
80%
20%
t_CLH
t_CHL
Figure 11. Deserializer LVCMOS/LVTTL Output Load and Transition Times
Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Links: DS99R103 DS99R104