DS99R103_13 Datasheet, PDF (14/29 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R103, DS99R104
SNLS241D – MARCH 2007 – REVISED APRIL 2013
DS99R104 Pin Diagram
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V_DDR1
37
V_SSR1
38
V_DDIR
39
V_SSIR
40
RIN+
41
RIN-
42
RRFB
43
V_SSPR1
44
V_DDPR1
45
V_SSPR0
46
V_DDPR0
47
REN
48
PTO GROUP 1
DS99R104
48 PIN WQFN
48 PIN TQFP
PTO GROUP 3
24
ROUT[8]
23
ROUT[9]
22
ROUT[10]
21
ROUT[11]
20
V_DDOR2
19
V_SSOR2
18
RCLK
17
LOCK
16
ROUT[12]
15
ROUT[13]
14
ROUT[14]
13
ROUT[15]
Figure 18. Deserializer - DS99R104
See Package Numbers NJU0048D (WQFN) and PFB0048A (TQFP)
DS99R104 Deserializer Pin Descriptions
Pin
No.
Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
25-28, ROUT[7:0]
31-34
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 1
13-16, ROUT[15:8]
21-24
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 2
3-6, 9- ROUT[23:16] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 3
12
18
RCLK
LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
43
RRFB
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
48
REN
LVCMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
1
RPWDNB
LVCMOS_I Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
14
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