DS99R103_13 Datasheet, PDF (12/29 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R103, DS99R104
SNLS241D – MARCH 2007 – REVISED APRIL 2013
DS99R103 Pin Diagram
Top View
www.ti.com
DIN[10]
37
DIN[11]
38
DIN[12]
39
DIN[13]
40
DIN[14]
41
V_DDIT
42
V_SSIT
43
DIN[15]
44
DIN[16]
45
DIN[17]
46
DIN[18]
47
DIN[19]
48
DS99R103
48 PIN WQFN
48 PIN TQFP
24
V_SS
23
PRE
22
V_DDDR
21
V_SSDR
20
DOUT+
19
DOUT-
18
DEN
17
V_SSPT0
16
V_DDPT0
15
V_SSPT1
14
V_DDPT1
13
RESRVD
Figure 17. Serializer - DS99R103
See Package Numbers NJU0048D (WQFN) and PFB0048A (TQFP)
DS99R103 Serializer Pin Descriptions
Pin
No.
Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
4-1, DIN[23:0]
48-44,
41-32,
29-25
LVCMOS_I Transmitter Parallel Interface Data Inputs Pins. Tie LOW if unused, do not float.
10
TCLK
LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin
CONTROL AND CONFIGURATION PINS
9
TPWDNB
LVCMOS_I Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs are
in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
18
DEN
LVCMOS_I
Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver DOUT (+/-) Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
23
PRE
LVCMOS_I
PRE-emphasis select pin.
PRE = (R_PRE ≥ 3 kΩ); I_max = [(1.2/R)*20], R_min = 3 kΩ
PRE = No Connect (NC); pre-emphasis is disabled
11
TRFB
LVCMOS_I
Transmitter Clock Edge Select Pin
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge.
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
12
Submit Documentation Feedback
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS99R103 DS99R104