DS99R103_13 Datasheet, PDF (5/29 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R103, DS99R104
www.ti.com
SNLS241D – MARCH 2007 – REVISED APRIL 2013
Electrical Characteristics^(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Pin/Freq.
SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs
I_DDT
Serializer (Tx)
Total Supply Current
(includes load current)
R_L = 100Ω
Pre-emphasis = OFF
VODSEL = L
Checker-board pattern (Figure 1)
f = 40 MHz
R_L = 100Ω
R_PRE = 6 kΩ
VODSEL = L
Checker-board pattern (Figure 1)
f = 40 MHz
Serializer (Tx)
Total Supply Current
(includes load current)
R_L = 100Ω
Pre-emphasis = OFF
VODSEL = H
Checker-board pattern (Figure 1)
f = 40 MHz
R_L = 100Ω
R_PRE = 6 kΩ
VODSEL = H
Checker-board pattern (Figure 1)
f = 40 MHz
I_DDTZ
Serializer (Tx)
TPWDNB = 0V
Supply Current Power-down (All other LVCMOS Inputs = 0V)
I_DDR
Deserializer (Rx)
Total Supply Current
(includes load current)
C_L = 8 pF LVCMOS Output
Checker-board pattern
(Figure 2)
f = 40 MHz
Deserializer (Rx)
Total Supply Current
(includes load current)
C_L = 8 pF LVCMOS Output
Random pattern
f = 40 MHz
I_DDRZ
Deserializer (Rx)
Supply Current Power-down
RPWDNB = 0V
(All other LVCMOS Inputs = 0V,
R_IN+/ R_IN-= 0V)
Min Typ Max Units
40 80 mA
45 85 mA
40 85 mA
45 90 mA
14 250 µA
95 mA
90 mA
1
50
µA
Serializer Timing Requirements for TCLK⁽¹⁾⁽²⁾
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min Typ Max Units
t_TCP
t_TCIH
t_TCIL
t_CLKT
t_JIT
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
(Figure 5)
(Figure 4)
See ⁽³⁾
25
0.4T
0.4T
T
0.5T
0.5T
3
333
ns
0.6T ns
0.6T ns
6
ns
33 ps (RMS)
(1) Figure 1, Figure 2, Figure 8, Figure 12, and Figure 14, show a falling edge data strobe (TCLK IN/RCLK OUT).
(2) Figure 5 and Figure 15 show a rising edge data strobe (TCLK IN/RCLK OUT).
(3) t_JIT (@BER of 10e-9) specifies the allowable jitter on TCLK. t_JIT not included in TxOUT_E_O parameter.
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min
t_LLHT
t_LHLT
LVDS Low-to-High Transition Time R_L = 100Ω, (Figure 3)
LVDS High-to-Low Transition Time
C_L = 10 pF to GND
VODSEL = L
t_DIS
DIN (23:0) Setup to TCLK
R_L = 100Ω,
5
t_DIH
DIN (23:0) Hold from TCLK
C_L = 10 pF to GND⁽¹⁾
5
Typ
Max Units
0.6
ns
0.6
ns
ns
ns
(1) Specification is ensured by characterization and is not tested in production.
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