DS99R103_13 Datasheet, PDF (17/29 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R103, DS99R104
www.ti.com
SNLS241D – MARCH 2007 – REVISED APRIL 2013
POWERDOWN
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power
when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into power down
mode, which reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is
driven low. In powerdown, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing
supply. To exit Powerdown, TPWDNB must be driven high. When the Serializer exits Powerdown, its PLL must
lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization before
data transfer can begin. The Deserializer enters powerdown mode when RPWDNB is driven low. In powerdown
mode, the PLL stops and the outputs enter TRI-STATE. To bring the Deserializer block out of the powerdown
state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and relock before data can be transferred. The Deserializer
will initialize and assert LOCK high when it is locked to the encoded clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN or TPWDNB pin is driven low. This will TRI-STATE both
driver output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer will return to the previous state
as long as all other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deserializer enters TRI-STATE. Consequently, the receiver
output pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the
state of the PLL. The Deserializer input pins are high impedance during receiver powerdown (RPWDNB low) and
power-off (V_DD = 0V).
PRE-EMPHASIS
The DS99R103 features a Pre-Emphasis mode used to compensate for long or lossy transmission media. Cable
drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output current during
transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media. Pre-Emphasis adds extra current during LVDS logic transition to reduce
the cable loading effects and increase driving distance. In addition, Pre-Emphasis helps provide faster
transitions, increased eye openings, and improved signal integrity. To enable the Pre-Emphasis function, the
“PRE” pin requires one external resistor (Rpre) to Vss in order to set the additional current level. Pre-Emphasis
strength is set via an external resistor (Rpre) applied from min to max (floating to 3kΩ) at the “PRE” pin. A lower
input resistor value on the ”PRE” pin increases the magnitude of dynamic current during data transition. There is
an internal current source based on the following formula: PRE = (Rpre ≥ 3kΩ); IMAX = [(1.2/Rpre) X 20]. The
ability of the DS99R103 to use the Pre-Emphasis feature will extend the transmission distance in most cases.
The amount of Pre-Emphasis for a given media will depend on the transmission distance of the application. In
general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This can result in
excessive noise, crosstalk and increased power dissipation. For short cables or distances, Pre-Emphasis may
not be required. Signal quality measurements are recommended to determine the proper amount of Pre-
Emphasis for each application.
AC-COUPLING AND TERMINATION
The DS99R103 and DS99R104 supports AC-coupled interconnects through integrated DC balanced
encoding/decoding scheme. To use AC coupled connection between the Serializer and Deserializer, insert
external AC coupling capacitors in series in the LVDS signal path as illustrated in Figure 19. The Deserializer
input stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal V_CM to
+1.2V. With AC signal coupling, capacitors provide the ac-coupling path to the signal input.
For the high-speed LVDS transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The most common
used capacitor value for the interface is 100 nF (0.1 µF) capacitor.
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS99R103 DS99R104
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