DS99R103_13 Datasheet, PDF (7/29 Pages) Texas Instruments – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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DS99R103, DS99R104
SNLS241D – MARCH 2007 – REVISED APRIL 2013
AC Timing Diagrams and Test Circuits
Device Pin Name
Signal Pattern
TCLK
ODD DIN
EVEN DIN
Figure 1. Serializer Input Checker-board Pattern
Device Pin Name
Signal Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 2. Deserializer Output Checker-board Pattern
DOUT+
10 pF
DOUT-
100:
Differential
80%
Signal _20%
10 pF
Vdiff = (DOUT+) - (DOUT-)
t_LLHT
80%
Vdiff = 0V
20%
t_LHLT
Figure 3. Serializer LVDS Output Load and Transition Times
TCLK
80%
20%
80%
20%
V_DD
0V
t_CLKT
t_CLK
Figure 4. Serializer Input Clock Transition Times
t_TCP
TCLK
V_DD/2
V_DD/2
V_DD/2
t_DIS
t_DIH
DIN [0:23] _VDD/2
Setup
Hold
V_DD/2
V_DD
0V
Figure 5. Serializer Setup/Hold Times
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