DS99R101_13 Datasheet, PDF (9/29 Pages) Texas Instruments – DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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DS99R101, DS99R102
SNLS240D – MARCH 2007 – REVISED APRIL 2013
24
DIN
DOUT+
R_L
DOUT-
TCLK
VOD = (D_OUT+) – (D_{OUT -})
Differential output signal is shown as (D_OUT+) – (D_{OUT -}), device in Data Transfer mode.
Figure 10. Serializer VOD Diagram
Deserializer
8 pF
lumped
Single-ended
Signal
80%
20%
80%
20%
t_CLH
t_CHL
Figure 11. Deserializer LVCMOS/LVTTL Output Load and Transition Times
RIN0-23
DCA, DCB
START
STOP START
STOP START
STOP START
STOP
BIT _{SYMBOL N} BIT BIT _{SYMBOL N+1} BIT BIT _{SYMBOL N+2} BIT BIT _{SYMBOL N+3} BIT
012
23
012
23
012
23
012
23
t_DD
RCLK
ROUT0-23
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
Figure 12. Deserializer Delay
SYMBOL N
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