DS99R101_13 Datasheet, PDF (13/29 Pages) Texas Instruments – DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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DS99R101 Pin Diagram
DS99R101, DS99R102
SNLS240D – MARCH 2007 – REVISED APRIL 2013
DIN[10]
37
DIN[11]
38
DIN[12]
39
DIN[13]
40
DIN[14]
41
V_DDIT
42
V_SSIT
43
DIN[15]
44
DIN[16]
45
DIN[17]
46
DIN[18]
47
DIN[19]
48
DS99R101
48 PIN TQFP
24
V_SS
23
NC
22
V_DDDR
21
V_SSDR
20
DOUT+
19
DOUT-
18
DEN
17
V_SSPT0
16
V_DDPT0
15
V_SSPT1
14
V_DDPT1
13
RESRVD
Figure 17. Serializer - DS99R101
TOP VIEW
DS99R102 Deserializer Pin Descriptions
Pin # Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
25-28, ROUT[7:0]
31-34
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 1
13-16, ROUT[15:8]
21-24
LVCMOS_O Receiver Parallel Interface Data Outputs – Group 2
3-6, 9- ROUT[23:16] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 3
12
18
RCLK
LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
43
RRFB
LVCMOS_I
Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
48
REN
LVCMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
1
RPWDNB
LVCMOS_I Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
17
LOCK
LVCMOS_O
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED
2
RESRVD
LVCMOS_I RESERVED – This pin MUST be tied LOW.
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13