DS99R101_13 Datasheet, PDF (4/29 Pages) Texas Instruments – DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101, DS99R102
SNLS240D – MARCH 2007 – REVISED APRIL 2013
Electrical Characteristics^(1)(2)(3) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min Typ
V_OD
Output Differential Voltage
R_L = 100Ω
(D_OUT+)–(D_OUT−)
VODSEL = L (Figure 10)
R_L = 100Ω
VODSEL = H (Figure 10)
Tx: D_OUT+, D_OUT−
250 400
450 750
ΔV_OD
Output Differential Voltage
Unbalance
R_L = 100Ω
4
V_OS
ΔV_OS
I_OS
Offset Voltage
Offset Voltage Unbalance
Output Short Circuit Current
R_L = 100Ω
R_L = 100Ω
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = L
1.00 1.25
1
−2 −5
DOUT = 0V, DIN = H,
TPWDNB, DEN = 2.4V,
VODSEL = H
−7 −10
I_OZ
TRI-STATE Output Current TPWDNB, DEN = 0V,
DOUT = 0V or 2.4V
SER/DES SUPPLY CURRENT (DVDD⁽⁵⁾, PVDD⁽⁵⁾ and AVDD⁽⁵⁾ pins)
−15 ±1
I_DDT
Serializer (Tx)
R_L = 100Ω
f = 40 MHz
Total Supply Current
VODSEL = L
40
(includes load current)
Checker-board pattern (Figure 1)⁽⁶⁾
R_L = 100Ω
f = 40 MHz
VODSEL = H
40
Checker-board pattern (Figure 1)⁽⁶⁾
I_DDTZ
Serializer (Tx)
Supply Current Power-down
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
1
I_DDR
Deserializer (Rx)
Total Supply Current
(includes load current)
C_L = 8 pF LVCMOS Output
Checker-board pattern
(Figure 2)⁽⁶⁾
f = 40 MHz
Deserializer (Rx)
Total Supply Current
(includes load current)
C_L = 8 pF LVCMOS Output
Random pattern
f = 40 MHz
I_DDRZ Deserializer (Rx)
RPWDNB = 0V
Supply Current Power-down (All other LVCMOS Inputs = 0V,
1
R_IN+/ R_IN-= 0V)
(5) Digital, PLL, and Analog VDDs
(6) Figure 1, Figure 2, Figure 8, Figure 12, Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
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Max Units
600 mV
1200 mV
50 mV
1.50 V
50 mV
−8 mA
−13 mA
+15 µA
80 mA
85 mA
100 µA
95 mA
90 mA
50
µA
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
t_TCP
t_TCIH
t_TCIL
t_CLKT
t_JIT
Parameter
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
Figure 5⁽¹⁾
Conditions
Figure 4
See ⁽²⁾
(1) Figure 5, Figure 15 show a rising edge data strobe (TCLK IN/RCLK OUT).
(2) t_JIT (@BER of 10e-9) specifies the allowable jitter on TCLK. t_JIT not included in TxOUT_E_O parameter.
Min
25
0.4T
0.4T
Typ
T
0.5T
0.5T
3
Max
333
0.6T
0.6T
6
33
Units
ns
ns
ns
ns
ps
(RMS)
4
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