DS99R101_13 Datasheet, PDF (5/29 Pages) Texas Instruments – DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101, DS99R102
www.ti.com
SNLS240D – MARCH 2007 – REVISED APRIL 2013
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_LLHT
t_LHLT
LVDS Low-to-High Transition Time
LVDS High-to-Low Transition Time
R_L = 100Ω, (Figure 3)
C_L = 10 pF to GND
VODSEL = L
t_DIS
DIN (23:0) Setup to TCLK
R_L = 100Ω,
5
t_DIH
DIN (23:0) Hold from TCLK
C_L = 10 pF to GND⁽¹⁾
5
t_HZD
DOUT ± HIGH to TRI-STATE Delay
R_L = 100Ω,
t_LZD
DOUT ± LOW to TRI-STATE Delay
C_L = 10 pF to GND
(Figure 6)⁽²⁾
t_ZHD
DOUT ± TRI-STATE to HIGH Delay
t_ZLD
DOUT ± TRI-STATE to LOW Delay
t_PLD
Serializer PLL Lock Time
t_SD
Serializer Delay
R_L = 100Ω, (Figure 7)
R_L = 100Ω, (Figure 8)⁽³⁾
VODSEL = L, TRFB = H
R_L = 100Ω, (Figure 8)⁽³⁾
VODSEL = L, TRFB = L
TxOUT_E_O
TxOUT_Eye_Opening
(respect to ideal)
3–40 MHz
(Figure 9)⁽⁴⁾
Typ
10
3.5T + 2.85
3.5T + 2.85
0.68
Max
0.6
0.6
15
15
200
200
3.5T
+ 10
3.5T
+ 10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
UI ⁽⁵⁾
(1) Specification is guaranteed by characterization and is not tested in production.
(2) When the Serializer output is at TRI-STATE, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
(3) Figure 1, Figure 2, Figure 8, Figure 12, Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
(4) t_JIT (@BER of 10e-9) specifies the allowable jitter on TCLK. t_JIT not included in TxOUT_E_O parameter.
(5) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
t_RCP
t_RDC
t_CLH
t_CHL
t_ROS
t_ROH
t_ROS
t_ROH
t_ROS
t_ROH
t_HZR
t_LZR
t_ZHR
t_ZLR
t_DD
Parameter
Receiver out Clock Period
RCLK Duty Cycle
Conditions
t_RCP = t_TCP ⁽¹⁾
LVCMOS Low-to-High
Transition Time
LVCMOS High-to-Low
Transition Time
ROUT (7:0) Setup Data to
RCLK (Group 1)
C_L = 8 pF
(lumped load)
(Figure 11)
(Figure 15)⁽²⁾
ROUT (7:0) Hold Data to RCLK
(Group 1)
ROUT (15:8) Setup Data to
RCLK (Group 2)
(Figure 15)⁽²⁾
ROUT (15:8) Hold Data to
RCLK (Group 2)
ROUT (23:16) Setup Data to
RCLK (Group 3)
(Figure 15)⁽²⁾
ROUT (23:16) Hold Data to
RCLK (Group 3)
HIGH to TRI-STATE Delay
(Figure 13)
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
(Figure 12)⁽³⁾
Pin/Freq.
RCLK
RCLK
ROUT [23:0],
LOCK, RCLK
ROUT [7:0]
ROUT [15:8],
LOCK
ROUT [23:16]
ROUT [23:0],
RCLK, LOCK
RCLK
Min
25
45
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
(0.40)*
t_RCP
Typ
T
50
2.5
2.5
(29/56)*t_RCP
(27/56)*t_RCP
0.5*t_RCP
0.5*t_RCP
(27/56)*t_RCP
(29/56)*t_RCP
3
3
3
3
[4+(3/56)]T
+5.9
Max
333
55
3.5
3.5
10
10
10
10
[4+(3/56)]T
+18.5
Units
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1) Specification is guaranteed by characterization and is not tested in production.
(2) Figure 5, Figure 15 show a rising edge data strobe (TCLK IN/RCLK OUT).
(3) Figure 1, Figure 2, Figure 8, Figure 12, Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
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