DS99R101_13 Datasheet, PDF (6/29 Pages) Texas Instruments – DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101, DS99R102
SNLS240D – MARCH 2007 – REVISED APRIL 2013
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
t_DRDL
Parameter
Deserializer PLL Lock Time
from Powerdown⁽⁴⁾
Conditions
(Figure 14) ⁽³⁾
(5) (1)
Pin/Freq.
3 MHz
40 MHz
Min
Typ
5
5
RxIN_TOL_L Receiver INput TOLerance
Left
(Figure 16)
(6) (1) (7)
3 MHz–40 MHz
RxIN_TOL_R Receiver INput TOLerance
Right
(Figure 16)
(6) (1) (7)
3 MHz–40 MHz
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Max
Units
50
ms
50
ms
0.25
UI
0.25
UI
(4) t_DRDL is the time required by the deserializer to obtain lock when exiting powerdown mode. t_DRDL is specified with an external
synchronization pattern.
(5) The Deserializer PLL lock time (t_DRDL) may vary depending on input data patterns and the number of transitions within the pattern.
(6) RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors
occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail.
(7) UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
AC Timing Diagrams and Test Circuits
Device Pin Name
Signal Pattern
TCLK
ODD DIN
EVEN DIN
Figure 1. Serializer Input Checker-board Pattern
Device Pin Name
Signal Pattern
RCLK
ODD ROUT
EVEN ROUT
Figure 2. Deserializer Output Checker-board Pattern
DOUT+
DOUT-
10 pF
100:
Differential
80%
Signal _20%
10 pF
Vdiff = (DOUT+) - (DOUT-)
t_LLHT
80%
Vdiff = 0V
20%
t_LHLT
Figure 3. Serializer LVDS Output Load and Transition Times
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