DS99R101_13 Datasheet, PDF (7/29 Pages) Texas Instruments – DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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DS99R101, DS99R102
SNLS240D – MARCH 2007 – REVISED APRIL 2013
TCLK
80%
20%
80%
V_DD
20%
0V
t_CLKT
t_CLK
Figure 4. Serializer Input Clock Transition Times
t_TCP
TCLK
V_DD/2
V_DD/2
V_DD/2
t_DIS
t_DIH
DIN [0:23] _VDD/2
Setup
Hold
V_DD/2
V_DD
0V
Figure 5. Serializer Setup/Hold Times
Parasitic package and
Trace capcitance
DEN VCC/2
(single-ended)
0V
DOUT±
(differential)
200 mV
DEN VCC/2
(single-ended)
0V
200 mV
DOUT±
(differential)
DEN
DOUT+
DOUT-
5 pF
100:
CLK1
t_LZD
V_CC/2
CLK1
t_TCP
t_TCP
t_ZLD
t_ZHD
DCA
DCA _{DCA DCA}
$OO GDWD ³0´V
DCA DCA DCA DCA
t_HZD
V_CC/2
DCA ^{DCA DCA DCA}
$OO GDWD ³1´V
DCA DCA DCA DCA
CLK0
t_TCP
t_TCP
CLK0
Figure 6. Serializer TRI-STATE Test Circuit and Delay
0V
200 mV
0V
200 mV
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