DS92LV3241_14 Datasheet, PDF (9/32 Pages) Texas Instruments – 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3241, DS92LV3242
www.ti.com
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
Electrical Characteristics⁽¹⁾⁽²⁾ (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
I_DDTD
Serializer (Tx) Total Supply Current
Dual Mode
(includes load current)
f= 50 MHz, CHECKER BOARD pattern
MODE = L, VSEL = H, PRE = OFF
f= 50 MHz, CHECKER BOARD pattern
MODE = H, VSEL = H, RPRE = 12 kΩ
f= 50 MHz, RANDOM pattern
MODE = L, VSEL = H, PRE = OFF
f= 50 MHz, RANDOM pattern
MODE = L, VSEL = H, RPRE = 12 kΩ
I_DDTZ
Serializer Supply Current
Power-down
TPWDNB = 0V
(All other LVCMOS Inputs = 0V)
DESERIALIZER LVDS DC SPECIFICATIONS
V_TH
Differential Threshold High Voltage
V_CM = +1.8V
V_TL
Differential Threshold Low Voltage
−50
R_T
Input Termination
Internal differential output termination
between differential pairs
90
I_IN
Input Current
V_IN = +2.4V, V_DD = 3.6V
V_IN = 0V, V_DD = 3.6V
DESERIALIZER SUPPLY CURRENT (DVDD, PVDD AND AVDD PINS)⁽⁴⁾
I_DDR
Deserializer Total Supply Current
f = 85 MHz, C_L = 8 pF,
(includes load current)
CHECKER BOARD pattern, Quad Mode
f = 85 MHz, C_L = 8 pF,
RANDOM pattern, Quad Mode
f = 50 MHz, C_L = 8 pF,
CHECKER BOARD pattern, Dual Mode
f = 50 MHz, C_L = 8 pF,
RANDOM pattern, Dual Mode
I_DDRZ
Deserializer Supply Current Power-down PDB = 0V
(All other LVCMOS Inputs = 0V,
RxIN[3:0](P/N) = 0V)
Typ
Max Units
120
145
120
145
mA
115
135
115
135
2
50
µA
+50
mV
mV
100
130
Ω
±100 ±250
µA
±100 ±250
µA
240
265
mA
190
210
145
185
mA
122
140
100
µA
(4) DIGITAL, PLL, AND ANALOG VDDS
Serializer Input Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
t_CIP
TxCLKIN Period
MODE = L (Dual Mode)
MODE = H (Quad Mode)
20
11.76
t_CIH
TxCLKIN High Time
t_TCIL
TxCLKIN Low Time
t_CIT
TxCLKIN Transition Time
20 MHz – 50 MHz
40 MHz – 85 MHz
20 MHz – 50 MHz
Figure 7
40 MHz – 85 MHz
20 MHz – 50 MHz
Figure 6
0.45 x
t_CIP
0.45 x
t_CIP
0.45 x
t_CIP
0.45 x
t_CIP
0.5
40 MHz – 85 MHz
0.5
t_JIT
TxCLKIN Jitter
Typ
t_CIP
t_CIP
0.5 x t_CIP
0.5 x t_CIP
0.5 x t_CIP
0.5 x t_CIP
Max
50
25
0.55 x
t_CIP
0.55 x
t_CIP
0.55 x
t_CIP
0.55 x
t_CIP
1.2
1.2
±100
Units
ns
ns
ns
ns
ps_P-P
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