DS92LV3241_14 Datasheet, PDF (17/32 Pages) Texas Instruments – 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3241, DS92LV3242
www.ti.com
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
When all of the DES channels obtain lock , the LOCK pin is driven high and synchronously delivers valid data
and recovered clock on the output. The DES locks to the clock, uses it to generate multiple internal data strobes,
and then drives the recovered clock to the RxCLKOUT pin. The recovered clock (RxCLKOUT) is synchronous to
the data on the RxOUT[31:0] pins. While LOCK is high, data on RxOUT[31:0] is valid. Otherwise, RxOUT[31:0] is
invalid. The polarity of the RxCLKOUT edge is controlled by its R_FB (DES) input. RxOUT[31:0], LOCK and
RxCLKOUT outputs will each drive a maximum of 8 pF load. REN controls TRI-STATE for RxOUT0–RxOUT31
and the RxCLKOUT pin on the DES.
RESYNCHRONIZATION
In the absence of data transitions on one of the channels into the DES (e.g. a loss of the link), it will automatically
try to resynchronize and re-establish lock using the standard lock sequence on the master channel (Channel 0).
For example, if the embedded clock is not detected one time in succession on any of the serial links, the LOCK
pin is driven low. The DES then monitors the master channel for lock, once that is obtained, the second channel
is locked and aligned. The logic state of the LOCK signal indicates whether the data on RxOUT is valid; when it
is high, the data is valid. The system may monitor the LOCK pin to determine whether data on the RxOUT is
valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the SER and DES may use to reduce power when no data
is being transferred. The respective PDB pins are used to set each device into power down mode, which reduces
supply current into the µA range. The SER enters Powerdown when the SER PDB pin is driven low. In
Powerdown, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing current
supply. To exit Powerdown, SER PDB must be driven high. When the SER exits Powerdown, its PLL must lock
to TxCLKIN before it is ready for sending data to the DES. The system must then allow time for the DES to lock
before data can be recovered.
The DES enters Powerdown mode when DES PDB is driven low. In Powerdown mode, the PLL’s stop and the
outputs enter TRI-STATE. To bring the DES block out of the Powerdown state, the system drives DES PDB high.
Both the SER and DES must relock before data can be transferred from Host and received by the Target. The
DES will startup and assert LOCK high when it is locked to the embedded clocks. See also Figure 13.
TRI-STATE
For the SER, TRI-STATE is entered when the SER PDB pin is driven low. This will TRI-STATE the driver output
pins on TxOUT[3:0]+/-. In addition, when MODE=0 (dual mode), the TxOUT[3:2]+/- outputs pins are in TRI-
STATE.
When you drive the REN or DES PDB pin low, the DES output pins (RxOUT[31:0]) and RxCLKOUT will enter
TRI-STATE. The LOCK output remains active, reflecting the state of the PLL. The DES input pins are high
impedance during receiver Powerdown (DES PDB low) and power-off (VDD = 0V). See also Figure 13.
TRANSMIT PARALLEL DATA AND CONTROL INPUTS
The DS92LV3241 operates on a core supply voltage of 3.3V with an optional digital supply voltage for 1.8V, low-
swing, input support. The SER single-ended (32-bit parallel data and control inputs) pins are 1.8V and 3.3V
LVCMOS logic level compatible and is configured through the IOVDD input supply rail. If 1.8V is required, the
IOVDD pin must be connected to a 1.8V supply rail. Also when power is applied to the transmitter, IOVDD pin
must be applied before or simultaneously with other power supply pins (3.3V). If 1.8V input swing is not required,
this pin should be tied to the common 3.3V rail. During normal operation, the voltage level on the IOVDD pins
must not change.
PRE-EMPHASIS
The SER LVDS Line Driver features a Pre-Emphasis function used to compensate for extra long or lossy
transmission media. The same amount of Pre-Emphasis is applied on all of the enabled differential output
channels. Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output
current during transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media.
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