DS92LV3241_14 Datasheet, PDF (21/32 Pages) Texas Instruments – 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3241, DS92LV3242
www.ti.com
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
There are eight power pins for the device. These may be bussed together on a common 3.3V plane (3.3V
LVCMOS I/O interface). If 1.8V input swing level for parallel data and control pins are required, connect the
IOVDD pin to 1.8V. At a minimum, eight 0.1uF capacitors should be used for local bypassing.
3.3V
3.3V
1.8V or 3.3V
VDDA
VDDPLL
VDDPLL
IOVDD
VDD
VDD
VDD
VDD
3.3V
TxCLKIN
VSS
VSS
TxIN31
VSS
TxIN30
VSS
TxIN29
TxIN28
VSSPLL
TxIN27
VSSPLL
TxIN26
TxIN25
VSSA
TxIN24
TxIN23
IOVSS
TxIN22
TxIN21
TxIN20
TxIN19
TxIN18
TxIN17
TxOUT0+
TxIN16
TxOUT0-
TxIN15
TxIN14
TxIN13
TxOUT1+
TxOUT1-
TxIN12
TxOUT2+
TxIN11
TxIN10
TxIN9
TxIN8
TxOUT2-
TxOUT3+
TxOUT3-
TxIN7
TxIN6
TxIN5
PRE
TxIN4
opt.
TxIN3
TxIN2
TxIN1
R_FB
TxIN0
VSEL
PDB
BISTEN
MODE
RSVD
Notes:
Caps are 0.1 PF
except Bulk Supply (4.7 PF)
Figure 20. DS92LV3241 Typical Connection Diagram
Figure 21 shows a typical application of the DS92LV3242 Deserializer (DES). The differential inputs utilize 100nF
coupling capacitors in the serial lines. Bypass capacitors are placed near the power supply pins. A system GPO
(General Purpose Output) controls the PDB pin. In this application the R_FB (DES) pin is tied Low to strobe the
data on the falling edge of the RxCLKOUT. The REN signal is not used and is tied High also.
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