DS92LV3241_14 Datasheet, PDF (20/32 Pages) Texas Instruments – 20-85 MHz 32-Bit Channel Link II Serializer / Deserializer

DS92LV3241, DS92LV3242
SNLS314D – SEPTEMBER 2009 – REVISED APRIL 2013
Recovered Pixel Clock
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BISTEN
Case 1: No bit errors
Recovered Pixel Data
Channel 0 - RxOUT0
Channel 1 - RxOUT8
Channel 2 ± RxOUT16
Channel 3 ± RxOUT24
Error counter
Channel 0 - RxOUT[7:1]
Channel 1 - RxOUT[15:9]
Channel 2 - RxOUT[23:17]
Channel 3 - RxOUT[31:25]
Case 2: Bit error(s)
Recovered Pixel Data
Channel 0 - RxOUT0
Channel 1 - RxOUT8
Channel 2 ± RxOUT16
Channel 3 ± RxOUT24
Error counter
Channel 0 - RxOUT[7:1]
Channel 1 - RxOUT[15:9]
Channel 2 - RxOUT[23:17]
Channel 3 - RxOUT[31:25]
Case 3: Bit error(s)
0
B
0
1
BB
0
B
23
4
Recovered Pixel Data
Channel 0 - RxOUT0
Channel 1 - RxOUT8
Channel 2 ± RxOUT16
Channel 3 ± RxOUT24
Error counter
Channel 0 - RxOUT[7:1]
Channel 1 - RxOUT[15:9]
0
Channel 2 - RxOUT[23:17]
Channel 3 - RxOUT[31:25]
B = Bad Bit
0
BIST Duration
44 x 10⁶ x t_CIP
Figure 19. BIST Diagram for Different Bit Error Cases
BIST PASS
0
BIST FAIL
4
B
BIST PASS
0
Status
Region
TYPICAL APPLICATION CONNECTION
Figure 20 shows a typical application of the DS92LV3241 Serializer (SER). The differential outputs utilize 100nF
coupling capacitors to the serial lines. Bypass capacitors are placed near the power supply pins. A system GPO
(General Purpose Output) controls the PDB and BISTEN pins. In this application the R_FB (SER) pin is tied Low
to latch data on the falling edge of the TxCLKIN. In this application the link is short, therefore the VSEL pin is tied
LOW for the standard output swing level. The Pre-emphasis input utilizes a resistor to ground to set the amount
of pre-emphasis desired by the application.
Configuration pins for the typical application are shown for SER:
• PDB – Power Down Control Input – Connect to host or tie HIGH (always ON)
• BISTEN – Mode Input - tie LOW if BIST mode is not used, or connect to host
• VSEL – tie LOW for normal VOD magnitude (application dependant)
• MODE – For clock rates between 20 MHz and 50 MHz tie LOW, for 40 MHz to 85 MHz tie HIGH
• PRE – Leave open if not required (have a R pad option on PCB)
• RSVD1 & RSVD2 – tie LOW
20
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