CD74ACT297_14 Datasheet, PDF (9/18 Pages) Texas Instruments – DIGITAL PHASE-LOCKED LOOP

CD74ACT297
DIGITAL PHASE-LOCKED LOOP
SCHS297D – AUGUST 1998 – REVISED JUNE 2002
φB
1.5 V
φA1
XORPD OUT
1.5 V
tPHL
1.5 V
tPLH
50% VCC 50% VCC 50% VCC
tPLH
1.5 V
3V
0V
tPHL
3V
0V
50% VCC
≈VCC
VOL
Figure 8. Phase Input (φB, φA2) to Output (XORPD OUT) Propagation Delays
3V
φB
1.5 V
1.5 V
0V
3V
φA2
1.5 V
0V
ECPD OUT
tPHL
50% VCC 50% VCC
tPLH
≈VCC
VOL
Figure 9. Phase Input (φB, φA2) to Output (ECPD OUT) Propagation Delays
ÎÎÎÎÎ _D/U
ÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏ _ENCTR
tH
1.5 V
1.5 V
1.5 V
tH
1.5 V
3V
(See Note A)
0V
tsu
tsu
3V
K CLK
1.5 V
1.5 V
1.5 V
0V
tw
1/fmax
NOTE A: Shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 10. Clock (K CLK) Pulse Duration and Maximum Clock-Pulse Frequency,
and Inputs (D/U, ENCTR) to Clock (K CLK) Setup and Hold Times
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