CD74ACT297_14 Datasheet, PDF (2/18 Pages) Texas Instruments – DIGITAL PHASE-LOCKED LOOP

CD74ACT297
DIGITAL PHASE-LOCKED LOOP
SCHS297D – AUGUST 1998 – REVISED JUNE 2002
description/ordering information (continued)
This device performs the classic first-order phase-locked-loop function without using analog components. The
accuracy of the digital phase-locked loop (DPLL) is not affected by V_CC and temperature variations, but depends
solely on accuracies of the K clock (K CLK), increment/decrement clock (I/D CLK), and loop propagation delays.
The I/D clock frequency and the divide-by-N modulos determine the center frequency of the DPLL. The center
frequency is defined by the relationship f_c = I/D clock/2N (Hz).
Modulo Controls
DC B A
14 15 1 2
4
K CLK ₆
D/U ₃
ENCTR
Modulo K
Counter
5
I/D CLK
φA1 ⁹
10
φB
13
φA2
Increment/Decrement
Circuit
J
K
7 _{I/D OUT}
11
XORPD OUT
12
ECPD OUT
Figure 1. Simplified Block Diagram
2
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