CD74ACT297_14 Datasheet, PDF (8/18 Pages) Texas Instruments – DIGITAL PHASE-LOCKED LOOP

CD74ACT297
DIGITAL PHASE-LOCKED LOOP
SCHS297D – AUGUST 1998 – REVISED JUNE 2002
Carry Pulse
(internal signal)
Borrow Pulse
(internal signal)
I/D CLK
I/D OUT
Figure 4. I/D OUT in Lock Condition
φB
φA2
ECPD OUT
Figure 5. Edge-Controlled Phase-Comparator Waveforms
φB
φA1
XORPD OUT
Figure 6. Exclusive-OR Phase-Detector Waveforms
I/D CLK
1/F max
tw
1.5 V
1.5 V
tPHL
90%
I/D OUT
10%
tTLH
50% VCC
tPHL
50% VCC
tTHL
3V
0V
≈VCC
VOL
Figure 7. Clock (ID CLK) to Output (ID OUT) Propagation Delays,
Clock Pulse Duration, and Maximum Clock-Pulse Frequency
8
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