CD74ACT297_14 Datasheet, PDF (6/18 Pages) Texas Instruments – DIGITAL PHASE-LOCKED LOOP

CD74ACT297
DIGITAL PHASE-LOCKED LOOP
SCHS297D – AUGUST 1998 – REVISED JUNE 2002
detailed description (continued)
Thus, the simple first-order phase-locked loop with an adjustable K counter is the equivalent of an analog
phase-locked loop with a programmable VCO gain.
Mfc
fout,
φ_out
fin,
φ_in
K CLK
D/U
ENCTR
XORPD OUT
φA1
φB
Divide-by-K
Counter
Carry
Borrow
J
ECPD
φA2
K
I/D OUT
Divide-by-N
Counter
I/D CLK
I/D Circuit
2 Nfc
Figure 3. DPLL Using Both Phase Detectors in a Ripple-Cancellation Scheme
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)^†
Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
DC input diode current, I_IK (V_I < –0.5 V or V_I > V_CC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
DC input diode current, I_OK (V_O < –0.5 V or V_O > V_CC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
DC output source or sink current per output pin, I_O (V_O > –0.5 V or V_O < V_CC + 0.5 V) . . . . . . . . . . ±50 mA
Continuous current through V_CC or GND (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θ_JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. For up to four outputs per device, add ±25 mA for each additional output.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
VCC
VIH
VIL
VI
VO
∆t/∆v
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
Input rise and fall slew rate
Operating free-air temperature range
MIN MAX UNIT
4.5 5.5 V
2
V
0.8 V
0 VCC V
0 VCC V
10 ns
–55 125 °C
6
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