CD74ACT297_14 Datasheet, PDF (5/18 Pages) Texas Instruments – DIGITAL PHASE-LOCKED LOOP

CD74ACT297
DIGITAL PHASE-LOCKED LOOP
SCHS297D – AUGUST 1998 – REVISED JUNE 2002
detailed description
The phase detector generates an error-signal waveform that, at zero phase error, is a 50% duty-cycle square wave.
At the limits of linear operation, the phase-detector output is either high or low all of the time, depending on the
direction of the phase error (φ_in – φ_out). Within these limits, the phase-detector output varies linearly with the input
phase error according to the gain k_d, which is expressed in terms of phase-detector output per cycle of phase error.
The phase-detector output can be varied between ±1 according to the relation:
+ Phase-detector output
% high – % low
100
(1)
The output of the phase detector is k_d φ_e, where the phase error φ_e = φ_in – φ_out.
XORPD and ECPD are commonly used digital types. The ECPD is more complex than the XORPD, but can be
described generally as a circuit that changes states on one of the transitions of its inputs. For an XORPD, k_d = 4,
because its output remains high (PD output = 1) for a phase error of one-fourth cycle. Similarly, for the ECPD,
k_d = 2, because its output remains high for a phase error of one-half cycle. The type of phase detector determines
the zero-phase-error point, i.e., the phase separation of the phase-detector inputs for φ_e is defined to be zero. For
the basic DPLL system of Figure 2, φ_e = 0 when the phase-detector output is a square wave. The XORPD inputs are
one-fourth cycle out of phase for zero phase error. For the ECPD, φ_e = 0 when the inputs are one-half cycle out of
phase.
Mfc
fin,
φ_in
fout,
φ_out
K CLK
D/U
Divide-by-K
Counter
XORPD OUT
φA1
φB
Carry
Borrow
I/D OUT
I/D Circuit
I/D CLK
Divide-by-N
Counter
2Nfc
Figure 2. DPLL Using Exclusive-OR Phase Detection
The phase-detector output controls the up/down input to the K counter. The counter is clocked by input frequency
Mf_c, which is a multiple M of the loop center frequency f_c. When the K counter recycles up, it generates a carry pulse.
Recycling while counting down generates a borrow pulse. If the carry and borrow outputs are conceptually combined
into one output that is positive for a carry and negative for a borrow, and if the K counter is considered as a frequency
divider with the ratio Mf_c/K, the output of the K counter equals the input frequency multiplied by the division ratio. Thus,
the output from the K counter is k_dφ_eMf_c/K.
The carry and borrow pulses go to the increment/decrement (I/D) circuit, which, in the absence of any carry or borrow
pulse, has an output that is one-half of the input clock (I/D CLK). The input clock is just a multiple (2N) of the loop
center frequency. In response to a carry or borrow pulse, the I/D circuit either adds or deletes a pulse at I/D OUT. Thus,
the output of the I/D circuit is Nf_c + (k_dφ_eMf_c)/2K.
The output of the N counter (or the output of the phase-locked loop) is:
+ ) ń fo fc (kdf_eMfc) 2KN
(2)
When this result is compared to the equation for a first-order analog phase-locked loop, the digital equivalent of the
gain of the VCO is Mf_c/2KN, or f_c/K for M = 2N.
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