BQ24725A_17 Datasheet, PDF (9/47 Pages) Texas Instruments – 1-4 Cell Li+ Battery SMBus Charge Controller with N-Channel Power MOSFET Selector and Advanced Circuit Protection

www.ti.com
bq24725A
SLUSAL0A – SEPTEMBER 2011 – REVISED AUGUST 2014
Electrical Characteristics (continued)
4.5 V ≤ V_VCC ≤ 24 V, 0°C ≤ T_J ≤ 125°C, typical values are at T_A = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
F_SW+
PWM increase frequency
F_SW–
PWM decrease frequency
BATFET GATE DRIVER (BATDRV)
ChargeOption() bit [10:9] = 11
ChargeOption() bit [10:9] = 01
665
885 1100
465
615
765
I_BATFET
V_BATFET
R_{BATDRV_LOAD}
BATDRV charge pump current limit
Gate drive voltage on BATFET
Minimum load resistance between
BATDRV and SRN
V_BATDRV - V_SRN when V_SRN > UVLO
40
60
5.5
6.1
6.5
500
R_{BATDRV_OFF}
BATDRV turn-off resistance
ACFET GATE DRIVER (ACDRV)
I = 30 µA
5
6.2
7.4
I_ACFET
V_ACFET
R_{ACDRV_LOAD}
ACDRV charge pump current limit
Gate drive voltage on ACFET
Minimum load resistance between ACDRV
and CMSRC
V_ACDRV–V_CMSRC when V_VCC> UVLO
40
60
5.5
6.1
6.5
500
R_{ACDRV_OFF}
V_{ACFET_LOW}
ACDRV turn-off resistance
ACDRV Turn-Off when Vgs voltage is low
(Specified by design)
I = 30 µA
5
6.2
7.4
5.9
PWM HIGH SIDE DRIVER (HIDRV)
R_{DS_HI_ON}
High side driver turn-on resistance
V_BTST – V_PH = 5.5 V, I = 10 mA
6
10
R_{DS_HI_OFF}
High side driver turn-off resistance
V_BTST – V_PH = 5.5 V, I = 10 mA
0.65
1.3
V_{BTST_REFRESH}
Bootstrap refresh comparator threshold
voltage
V_BTST – V_PH when low side refresh pulse is requested
3.85
4.3
4.7
PWM LOW SIDE DRIVER (LODRV)
R_{DS_LO_ON}
Low side driver turn-on resistance
R_{DS_LO_OFF}
Low side driver turn-off resistance
PWM DRIVER TIMING
V_REGN = 6 V, I = 10 mA
V_REGN = 6 V, I = 10 mA
7.5
12
0.9
1.4
t_{LOW_HIGH}
Driver dead time from low side to high side
20
t_{HIGH_LOW}
Driver dead time from high side to low side
20
INTERNAL SOFT START
I_STEP
Soft start current step
In CCM mode 10mΩ current sensing resistor
64
t_STEP
Soft start current step time
240
SMBus TIMING CHARACTERISTICS
t_R
SCLK/SDATA rise time
t_F
SCLK/SDATA fall time
t_W(H)
SCLK pulse width high
t_W(L)
SCLK Pulse Width Low
t_SU(STA)
Setup time for START condition
t_H(STA)
START condition hold time after which first clock pulse is generated
t_SU(DAT)
Data setup time
t_H(DAT)
Data hold time
t_SU(STOP)
Setup time for STOP condition
t_(BUF)
Bus free time between START and STOP condition
F_S(CL)
Clock Frequency
HOST COMMUNICATION FAILURE
1
300
4
50
4.7
4.7
4
250
300
4
4.7
10
100
t_timeout
t_BOOT
t_WDI
SMBus bus release timeout⁽²⁾
Deglitch for watchdog reset signal
Watchdog timeout period, ChargeOption() bit [14:13] = 01⁽³⁾
Watchdog timeout period, ChargeOption() bit [14:13] = 10⁽³⁾
Watchdog timeout period, ChargeOption() bit [14:13] = 11⁽³⁾ (Default)
25
35
10
35
44
53
70
88
105
140
175
210
UNIT
kHz
kHz
µA
V
kΩ
kΩ
μA
V
kΩ
kΩ
V
Ω
Ω
V
Ω
Ω
ns
ns
mA
μs
μs
ns
μs
μs
μs
μs
ns
ns
µs
μs
kHz
ms
ms
s
s
s
(2) Devices participating in a transfer will timeout when any clock low exceeds the 25ms minimum timeout period. Devices that have
detected a timeout condition must reset the communication no later than the 35ms maximum timeout period. Both a master and a slave
must adhere to the maximum value specified as it incorporates the cumulative stretch limit for both a master (10ms) and a slave (25ms).
(3) User can adjust threshold via SMBus ChargeOption() REG0x12.
Copyright © 2011–2014, Texas Instruments Incorporated
Product Folder Links: bq24725A
Submit Documentation Feedback
9