MSP430F5438A Datasheet, PDF (88/106 Pages) Texas Instruments – Mixed Signal Microcontroller

MSP430F5438A, MSP430F5437A, MSP430F5436A, MSP430F5435A
MSP430F5419A, MSP430F5418A
SLAS655D – JANUARY 2010 – REVISED AUGUST 2013
Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
P10REN.x
Pad Logic
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P10DIR.x
P10OUT.x
Module X OUT
P10SEL.x
P10IN.x
Module X IN
0
1
0
1
EN
D
Direction
0: Input
1: Output
DV_SS
0
DV_CC
1
1
P10DS.x
0: Low drive
1: High drive
P10.0/UCB3STE/UCA3CLK
P10.1/UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
P10.3/UCB3CLK/UCA3STE
P10.4/UCA3TXD/UCA3SIMO
P10.5/UCA3RXD/UCA3SOMI
P10.6
P10.7
PIN NAME (P10.x)
P10.0/UCB3STE/UCA3CLK
P10.1/UCB3SIMO/UCB3SDA
P10.2/UCB3SOMI/UCB3SCL
P10.3/UCB3CLK/UCA3STE
P10.4/UCA3TXD/UCA3SIMO
P10.5/UCA3RXD/UCA3SOMI
P10.6
P10.7
Table 57. Port P10 (P10.0 to P10.7) Pin Functions
x
FUNCTION
0 P10.0 (I/O)
UCB3STE/UCA3CLK^{(2) (3)}
1 P10.1 (I/O)
UCB3SIMO/UCB3SDA^{(2) (4)}
2 P10.2 (I/O)
UCB3SOMI/UCB3SCL ^{(2) (4)}
3 P10.3 (I/O)
UCB3CLK/UCA3STE^{(2) (5)}
4 P10.4 (I/O)
UCA3TXD/UCA3SIMO ⁽²⁾
5 P10.5 (I/O)
UCA3RXD/UCA3SOMI ⁽²⁾
6 P10.6 (I/O)
Reserved ⁽⁶⁾
7 P10.7 (I/O)
Reserved ⁽⁶⁾
CONTROL BITS/SIGNALS⁽¹⁾
P10DIR.x
P10SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
x
1
(1) X = Don't care
(2) The pin direction is controlled by the USCI module.
(3) UCA3CLK function takes precedence over UCB3STE function. If the pin is required as UCA3CLK input or output, USCI_B3 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(4) If the I2C functionality is selected, the output drives only the logical 0 to V_SS level.
(5) UCB3CLK function takes precedence over UCA3STE function. If the pin is required as UCB3CLK input or output, USCI A3 is forced to
3-wire SPI mode if 4-wire SPI mode is selected.
(6) The secondary function on these pins are reserved for factory test purposes. Application should keep the P10SEL.x of these ports
cleared to prevent potential conflicts with the application.
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