LM3S9D96 Datasheet, PDF (850/1407 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Inter-Integrated Circuit Sound (I²S) Interface
Bit/Field
25:24
23
22
21:16
15:10
9:4
3:0
Name
WM
FMT
MSL
reserved
SSZ
SDSZ
reserved
Type
R/W
R/W
R/W
RO
R/W
R/W
RO
Reset
0x0
Description
Write Mode
This bit field selects the mode in which the transmit data is stored in the
FIFO and transmitted.
Value Description
0x0 Stereo mode
0x1 Compact Stereo mode
Left/Right sample packed. Refer to I2STXFIFOCFG for 8/16-bit
sample size selection.
0x2 Mono mode
0x3 reserved
0
FIFO Empty
Value Description
0 All zeroes are transmitted if the FIFO is empty.
1 The last sample is transmitted if the FIFO is empty.
0
SCLK Master/Slave
Source of serial bit clock (I2S0TXSCK) and Word Select (I2S0TXWS).
Value Description
0 The transmitter is a slave using the externally driven I2S0TXSCK
and I2S0TXWS signals.
1 The transmitter is a master using the internally generated
I2S0TXSCK and I2S0TXWS signals.
0x00
0x1F
0x1F
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Sample Size
This field contains the number of bits minus one in the sample.
Note: This field is only used in Right-Justified mode. Unused bits
are not masked.
System Data Size
This field contains the number of bits minus one during the high or low
phase of the I2S0TXWS signal.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
850
January 23, 2012
Texas Instruments-Production Data