LM3S9D96 Datasheet, PDF (1260/1407 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Signal Tables
Table 24-3. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
USB0ID
66
PB0
I
Analog This signal senses the state of the USB ID signal.
The USB PHY enables an integrated pull-up, and
an external element (USB connector) indicates the
initial state of the USB controller (pulled down is
the A side of the cable and pulled up is the B side).
USB0PFLT
22
PC7 (6)
I
23
PC6 (7)
35
PA7 (8)
65
PB3 (8)
74
PE0 (9)
76
PH4 (4)
87
PJ1 (9)
TTL
Optionally used in Host mode by an external power
source to indicate an error state by that power
source.
USB0RBIAS
73
fixed
O
Analog 9.1-kΩ resistor (1% precision) used internally for
USB analog circuitry.
USB0VBUS
67
PB1
I/O
Analog This signal is used during the session request
protocol. This signal allows the USB PHY to both
sense the voltage level of VBUS, and pull up VBUS
momentarily during VBUS pulsing.
VDD
8
fixed
-
Power Positive supply for I/O and some logic.
20
32
44
56
68
81
93
VDDA
3
fixed
-
Power The positive supply for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from VDD to minimize the electrical noise contained
on VDD from affecting the analog functions. VDDA
pins must be supplied with a voltage that meets the
specification in Table 26-2 on page 1317, regardless
of system implementation.
VDDC
38
fixed
88
-
Power Positive supply for most of the logic function,
including the processor core and most peripherals.
The voltage on this pin is 1.3 V and is supplied by
the on-chip LDO. The VDDC pins should only be
connected to the LDO pin and an external capacitor
as specified in Table 26-6 on page 1322.
VREFA
90
PB6
I
Analog This input provides a reference voltage used to
specify the input voltage at which the ADC converts
to a maximum value. In other words, the voltage
that is applied to VREFA is the voltage with which
an AINn signal is converted to 4095. The VREFA
input is limited to the range specified in Table
26-23 on page 1333 .
XTALNPHY
17
fixed
O
Analog Ethernet PHY XTALN 25-MHz oscillator crystal
output. Leave this pin unconnected when using a
single-ended 25-MHz clock input connected to the
XTALPPHY pin.
XTALPPHY
16
fixed
I
Analog Ethernet PHY XTALP 25-MHz oscillator crystal
input or external clock reference input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
1260
Texas Instruments-Production Data
January 23, 2012