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AM1802 Datasheet, PDF (85/180 Pages) Texas Instruments – AM1802 ARM Microprocessor | |||
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AM1802
www.ti.com
SPRS710C â NOVEMBER 2010 â REVISED MARCH 2012
5.11 DDR2/mDDR Controller
The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports
JESD79-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.
The DDR2/mDDR Memory Controller support the following features:
⢠JESD79-2A standard compliant DDR2 SDRAM
⢠Mobile DDR SDRAM
⢠512 MByte memory space for DDR2
⢠256 MByte memory space for mDDR
⢠CAS latencies:
â DDR2: 2, 3, 4 and 5
â mDDR: 2 and 3
⢠Internal banks:
â DDR2: 1, 2, 4 and 8
â mDDR:1, 2 and 4
⢠Burst length: 8
⢠Burst type: sequential
⢠1 chip select (CS) signal
⢠Page sizes: 256, 512, 1024 and 2048
⢠SDRAM autoinitialization
⢠Self-refresh mode
⢠Partial array self-refresh (for mDDR)
⢠Power down mode
⢠Prioritized refresh
⢠Programmable refresh rate and backlog counter
⢠Programmable timing parameters
⢠Little endian
5.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
Table 5-23. Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR
Memory Controller
No.
PARAMETER
1
tc(DDR_CLK)
Cycle time,
DDR_CLKP / DDR_CLKN
(1) DDR2 is not supported at this voltage operating point.
DDR2
mDDR
1.2V
MIN MAX
125
156
105
150
1.1V
MIN MAX
125
150
100
133
1.0V
MIN
â (1)
MAX
â (1)
95
133
UNIT
MHz
Copyright © 2010â2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
85
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