AM1802 Datasheet, PDF (2/180 Pages) Texas Instruments – AM1802 ARM Microprocessor

AM1802
SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012
Timers)
• Packages:
– 361-Ball Pb-Free Plastic Ball Grid Array
(PBGA) [ZCE Suffix], 0.65-mm Ball Pitch
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– 361-Ball Pb-Free Plastic Ball Grid Array
(PBGA) [ZWT Suffix], 0.80-mm Ball Pitch
• Industrial Temperature
1.2 Description
The device is a low-power applications processor based on ARM926EJ-S™.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance life through the maximum
flexibility of a fully integrated mixed processor solution.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-
byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also
has a 8KB RAM (Vector Table) and 64KB ROM.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output
(MDIO) module; one USB2.0 OTG interface; one inter-integrated circuit (I2C) Bus interfaces; one
multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two SPI interfaces with
multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as
watchdog) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable
interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each with
RTS and CTS); and 2 external memory interfaces: an asynchronous and SDRAM external memory
interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and a
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is
available for PHY configuration. The EMAC supports both MII and RMII interfaces.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The device has a complete set of development tools for the ARM . These include C compilers, and
scheduling, and a Windows™ debugger interface for visibility into source code execution.
2
Device Summary
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