AM1802 Datasheet, PDF (1/180 Pages) Texas Instruments – AM1802 ARM Microprocessor

AM1802
www.ti.com
SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012
AM1802 ARM Microprocessor
Check for Samples: AM1802
1 Device Summary
1.1 Features
12
• Highlights
• NOR (8-/16-Bit-Wide Data)
– 300-MHz ARM926EJ-S™ RISC Core
• NAND (8-/16-Bit-Wide Data)
– ARM9 Memory Architecture
– Enhanced Direct-Memory-Access Controller
3 (EDMA3)
• 16-Bit SDRAM With 128 MB Address
Space
– DDR2/Mobile DDR Memory Controller
– Two External Memory Interfaces
– Three Configurable 16550 type UART
Modules
– Two Serial Peripheral Interfaces (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
• 16-Bit DDR2 SDRAM With 512 MB
Address Space or
• 16-Bit mDDR SDRAM With 256 MB
Address Space
• Three Configurable 16550 type UART Modules:
– With Modem Control Signals
– One Master/Slave Inter-Integrated Circuit
– 16-byte FIFO
– USB 2.0 OTG Port With Integrated PHY
– 16x or 13x Oversampling Option
– One Multichannel Audio Serial Port
– 10/100 Mb/s Ethernet MAC (EMAC)
– Three 64-Bit General-Purpose Timers
– One 64-bit General-Purpose/Watchdog Timer
• Two Serial Peripheral Interfaces (SPI) Each
With Multiple Chip-Selects
• One Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Interfaces
• One Master/Slave Inter-Integrated Circuit (I²C
Bus™)
• 300-MHz ARM926EJ-S RISC MPU
• USB 2.0 OTG Port With Integrated PHY (USB0)
• ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb^®) Instructions
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– Single Cycle MAC
– ARM^® Jazelle^® Technology
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
– EmbeddedICE-RT™ for Real-Time Debug
ISOC) Rx and Tx
• ARM9 Memory Architecture
• One Multichannel Audio Serial Port:
– 16K-Byte Instruction Cache
– Transmit/Receive Clocks
– 16K-Byte Data Cache
– Two Clock Zones and 16 Serial Data Pins
– 8K-Byte RAM (Vector Table)
– Supports TDM, I2S, and Similar Formats
– 64K-Byte ROM
– DIT-Capable
• Enhanced Direct-Memory-Access Controller 3
– FIFO buffers for Transmit and Receive
(EDMA3):
• 10/100 Mb/s Ethernet MAC (EMAC):
– 2 Channel Controllers
– IEEE 802.3 Compliant
– 3 Transfer Controllers
– MII Media Independent Interface
– 64 Independent DMA Channels
– RMII Reduced Media Independent Interface
– 16 Quick DMA Channels
– Management Data I/O (MDIO) Module
– Programmable Transfer Burst Size
• Real-Time Clock With 32-kHz Oscillator and
• 128K-Byte On-chip Memory
Separate Power Rail
• 1.8V or 3.3V LVCMOS IOs (except for USB and
• Three 64-Bit General-Purpose Timers (Each
DDR2 interfaces)
Configurable as Two 32-Bit Timers)
• Two External Memory Interfaces:
• One 64-Bit General-Purpose/Watchdog Timer
– EMIFA
(Configurable as Two 32-Bit General-Purpose
1
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2
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