AM1802 Datasheet, PDF (29/180 Pages) Texas Instruments – AM1802 ARM Microprocessor

AM1802
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SPRS710C – NOVEMBER 2010 – REVISED MARCH 2012
2.7.14 Ethernet Media Access Controller (EMAC)
Table 2-16. Ethernet Media Access Controller (EMAC) Terminal Functions
SIGNAL
NAME
TYPE ⁽¹⁾
NO.
PULL ⁽²⁾
POWER
GROUP ⁽³⁾
DESCRIPTION
MII
AXR6 / GP1[14] / MII_TXEN
C1
O
CP[5]
A
EMAC MII Transmit enable output
AXR5 / GP1[13] / MII_TXCLK
D3
I
CP[5]
A
EMAC MII Transmit clock input
AXR4 / GP1[12] / MII_COL
D1
I
CP[5]
A
EMAC MII Collision detect input
AXR3 / GP1[11] / MII_TXD[3]
E3
O
CP[5]
A
AXR2 / GP1[10] / MII_TXD[2]
AXR1 / GP1[9] / MII_TXD[1]
E2
O
E1
O
CP[5]
CP[5]
A
EMAC MII transmit data
A
AXR0 / GP8[7] / MII_TXD[0]
F3
O
CP[6]
A
SPI0_SOMI / GP8[6] / MII_RXER
C16
I
CP[7]
A
EMAC MII receive error input
SPI0_SIMO / GP8[5] / MII_CRS
C18
I
CP[7]
A
EMAC MII carrier sense input
SPI0_CLK / GP1[8] / MII_RXCLK
D19
I
CP[7]
A
EMAC MII receive clock input
SPI0_ENA / MII_RXDV
C17
I
CP[7]
A
EMAC MII receive data valid input
SPI0_SCS[5] / UART0_RXD / GP8[4] / MII_RXD[3] C19
I
CP[8]
A
SPI0_SCS[4] / UART0_TXD / GP8[3] / MII_RXD[2]
D18
I
SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1]
E17
I
CP[8]
CP[9]
A
EMAC MII receive data
A
SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0]
D16
I
CP[9]
A
RMII
RMII_MHZ_50_CLK
W18 I/O
CP[26]
C
EMAC 50-MHz clock input or output
RMII_RXER
W17
I
CP[26]
C
EMAC RMII receiver error
RMII_RXD[0]
RMII_RXD[1]
V17
I
W16
I
CP[26]
CP[26]
C
EMAC RMII receive data
C
RMII_CRS_DV
W19
I
CP[26]
C
EMAC RMII carrier sense data valid
RMII_TXEN
R14
O
CP[26]
C
EMAC RMII transmit enable
RMII_TXD[0]
RMII_TXD[1]
V16
O
U18
O
CP[26]
CP[26]
C
EMAC RMII transmit data
C
MDIO
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / MDIO_D /
TM64P1_IN12
D17
I/O
CP[10]
A
MDIO serial data
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / MDIO_CLK
/ TM64P0_IN12
E16
O
CP[10]
A
MDIO clock
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,
an external pull-up can be used. For electrical specifications on the pull-up and and internal pull-down circuits, see the Device Operating
Conditions section.
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power
supply DVDD3318_C.
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