LM3S5P51 Datasheet, PDF (833/1260 Pages) Texas Instruments – Stellaris® LM3S5P51 Microcontroller

Stellaris^® LM3S5P51 Microcontroller
Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x008
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RP
REC
TEC
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:16
15
Name
reserved
RP
Type
RO
RO
Reset
0x0000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Received Error Passive
Value
0
1
Description
The Receive Error counter is below the Error Passive
level (127 or less).
The Receive Error counter has reached the Error Passive
level (128 or greater).
14:8
REC
RO
0x00 Receive Error Counter
This field contains the state of the receiver error counter (0 to 127).
7:0
TEC
RO
0x00 Transmit Error Counter
This field contains the state of the transmit error counter (0 to 255).
January 21, 2012
833
Texas Instruments-Production Data