LM3S5P51 Datasheet, PDF (1078/1260 Pages) Texas Instruments – Stellaris® LM3S5P51 Microcontroller

Pulse Width Modulator (PWM)
Bit/Field
2
1
0
Name
FAULT2
FAULT1
FAULT0
Type
-
-
-
Reset
0
Description
Fault Input 2
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the FAULT2 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is R/W1C and
represents a sticky version of the FAULT2 input signal after the logic
sense adjustment.
■ If FAULT2 is set, the input transitioned to the active state previously.
■ If FAULT2 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■ The FAULT2 bit is cleared by writing it with the value 1.
0
Fault Input 1
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the FAULT1 input signal after the logic sense
adjustment.
If the PWMnCTL register LATCH bit is set, this bit is R/W1C and
represents a sticky version of the FAULT1 input signal after the logic
sense adjustment.
■ If FAULT1 is set, the input transitioned to the active state previously.
■ If FAULT1 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■ The FAULT1 bit is cleared by writing it with the value 1.
0
Fault Input 0
If the PWMnCTL register LATCH bit is clear, this bit is RO and represents
the current state of the input signal after the logic sense adjustment.
If the PWMnCTL register LATCH bit is set, this bit is R/W1C and
represents a sticky version of the input signal after the logic sense
adjustment.
■ If FAULT0 is set, the input transitioned to the active state previously.
■ If FAULT0 is clear, the input has not transitioned to the active state
since the last time it was cleared.
■ The FAULT0 bit is cleared by writing it with the value 1.
1078
Texas Instruments-Production Data
January 21, 2012