LM3S5P51 Datasheet, PDF (628/1260 Pages) Texas Instruments – Stellaris® LM3S5P51 Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Table 13-2. UART Signals (108BGA) (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
U1DCD
B1
PE7 (9)
I
G2
PD1 (9)
M6
PA7 (9)
TTL
UART module 1 Data Carrier Detect modem status
input signal.
U1DSR
M9
PF0 (9)
I
TTL
UART module 1 Data Set Ready modem output
control line.
U1DTR
M7
PG5 (10)
O
A2
PD7 (9)
TTL
UART module 1 Data Terminal Ready modem
status input signal.
U1RI
L7
PG6 (10)
I
K3
PG4 (10)
B5
PD4 (9)
TTL
UART module 1 Ring Indicator modem status input
signal.
U1RTS
M8
PF6 (10)
O
H12
PF1 (9)
TTL
UART module 1 Request to Send modem flow
control output line.
U1Rx
G1
PD0 (5)
I
H2
PD2 (1)
M2
PC6 (5)
L3
PA0 (9)
E12
PB0 (5)
A6
PB4 (7)
TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Tx
G2
PD1 (5)
O
H1
PD3 (1)
L2
PC7 (5)
M3
PA1 (9)
D12
PB1 (5)
B7
PB5 (7)
TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Rx
G1
PD0 (4)
I
K1
PG0 (1)
A6
PB4 (4)
C6
PD5 (9)
TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Tx
B2
PE4 (5)
O
G2
PD1 (4)
K2
PG1 (1)
A3
PD6 (9)
TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3
Functional Description
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 653). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to
an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
13.3.1
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits
628
January 21, 2012
Texas Instruments-Production Data