LM3S5P51 Datasheet, PDF (304/1260 Pages) Texas Instruments – Stellaris® LM3S5P51 Microcontroller

Hibernation Module
6.4.4
6.4.5
6.5
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the
HIBCTL register at offset 0x010.
External Wake-Up from Hibernation
Use the following steps to implement the Hibernation module with the external WAKE pin as the
wake-up source for the microcontroller:
1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the
HIBCTL register at offset 0x010.
Note that in this mode, if the RTC is disabled, then the Hibernation clock source is powered down
during Hibernate mode and is powered up again on the external wake event to save power during
hibernation. If the RTC is enabled before hibernation, it continues to operate during hibernation.
RTC or External Wake-Up from Hibernation
1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008.
2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C.
3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C.
4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F
to the HIBCTL register at offset 0x010.
Register Map
Table 6-4 on page 305 lists the Hibernation registers. All addresses given are relative to the Hibernation
Module base address at 0x400F.C000. Note that the system clock to the Hibernation module must
be enabled before the registers can be programmed (see page 265). There must be a delay of 3
system clocks after the Hibernation module clock is enabled before any Hibernation module registers
are accessed.
Note:
HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the
Hibernation module clock domain and have special timing requirements. Software should
make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has
elapsed. If the WRC bit is clear, any attempted write access is ignored. See “Register Access
Timing” on page 297.
Important: The Hibernation module registers are reset under two conditions:
1. A system reset when the RTCEN and the PINWEN bits in the HIBCTL register are
both cleared.
2. A cold POR, when both the V_DD and V_BAT supplies are removed.
Any other reset condition is ignored by the Hibernation module.
304
January 21, 2012
Texas Instruments-Production Data