LM3S5P51 Datasheet, PDF (553/1260 Pages) Texas Instruments – Stellaris® LM3S5P51 Microcontroller

Stellaris^® LM3S5P51 Microcontroller
number of samples in the averaging calculation. For example, if the averaging circuit is configured
to average 16 samples, the throughput is decreased by a factor of 16.
By default the averaging circuit is off, and all data from the converter passes through to the sequencer
FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC)
register (see page 590). A single averaging circuit has been implemented, thus all input channels
receive the same amount of averaging whether they are single-ended or differential.
Figure 12-6 shows an example in which the ADCSAC register is set to 0x2 for 4x hardware
oversampling and the IE1 bit is set for the sample sequence, resulting in an interrupt after the
second averaged value is stored in the FIFO.
Figure 12-6. Sample Averaging Example
A+B+C+D
4
A+B+C+D
4
INT
12.3.4
Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) module uses a Successive Approximation Register (SAR)
architecture to deliver a 10-bit, low-power, high-precision conversion value. The
successive-approximation algorithm uses a current mode D/A converter to achieve lower settling
time, resulting in higher conversion speeds for the A/D converter. In addition, built-in sample-and-hold
circuitry with offset-calibration circuitry improves conversion accuracy. The ADC must be run from
the PLL or a 16-MHz clock source. Figure 12-7 shows the ADC input equivalency diagram; for
parameter values, see “Analog-to-Digital Converter (ADC)” on page 1191.
January 21, 2012
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