TM4C1292NCPDT Datasheet, PDF (829/1822 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1292NCPDT Microcontroller
The RDYEN in the EPIHBnCFG enables the monitoring of the external iRDY pin to stall accesses.
On the rising edge of EPI clock, if iRDY is low, access is stalled. The IRDYDLY can program the
number of EPI clock cycles in advance to the stall (1,2 or 3) as shown in Figure 11-5 on page 829.
This is a conceptual timing diagram of how the iRDY signal works with different IRDYDLY
configurations. When enabled, the iRDY stalls the EPI's internal states, while IRDYDLY controls the
delay pipeline when this stall takes affect. The iRDY signal can be connected to multiple devices
with a pull up resistor as shown in Figure 11-6 on page 829. Note that when multiple PSRAMs are
connected to iRDY, the EPIHPnCFG registers must be programmed to the same iRDY signal polarity
through the IRDYINV bit. When connected to a PSRAM, iRDY is used to control the address to
data latency.
Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11
CLOCK
(EPI0S31)
IRDY
(EPI0S32)
State
Data A
Data B
Data C
Data D
Data E
Data F
IRDYDLY=01
Data A
Data B
Data C
Data D
Data E
IRDYDLY=10
Data A
Data B
Data C
Data D
Data E
IRDYDLY=11
Data A
Data B
Data C
Data D
Data E
Figure 11-6. iRDY Signal Connection
IRDY
Cellular RAM
WAIT
Processor
WAIT
Other
Device
WAIT
Other
Device
11.4.3.2
PSRAM Support
The EPI Host Bus supports both a synchronous and asynchronous interface to PSRAM memory
when configured in 16-bit bus multiplexed mode. The EPIHBPSRAM register holds the values for
the PSRAM's bus configuration registers (CR). The contents of the EPIHBPSRAM register can be
sent to different memories depending on which WRCRE or RDCRE bit is set in the various
EPIHB16CFGn registers. For example, if the WRCRE bit is enabled in EPIHB16CFG, then the CRE
signal asserts and the contents are sent to the memory enabled by CS0. Enabling the WRCRE or
RDCRE bit in EPIHB16CFG2 register activates CS1n during a PSRAM configuration register write
or read. The WRCRE and RDCRE bit in EBIHB16CFG3 corresponds to CS2n and EPIHB16CFG4, to
CS3n. The WRCRE bit clears when the transfer is done. There must not be any system access or
June 18, 2014
829
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