TM4C1292NCPDT Datasheet, PDF (1140/1822 Pages) Texas Instruments – Tiva Microcontroller

Analog-to-Digital Converter (ADC)
Register 46: ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3),
offset 0x0BC
This register controls the sample period size for the sample in sequencer 3. The sample and hold
period select specifies the time allocated to the sample and hold circuit as shown by the encodings
in Table 15-3 on page 1051
Note: If sampling the internal temperature sensor, the sample and hold width should be at least
16 ADC clocks (TSHn = 0x4).
Table 15-10. Sample and Hold Width in ADC Clocks
TSHn Encoding
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD-0xF
N_SH
4
reserved
8
reserved
16
reserved
32
reserved
64
reserved
128
reserved
256
reserved
ADC Sample Sequence 3 Sample and Hold Time (ADCSSTSH3)
ADC0 base: 0x4003.8000
ADC1 base: 0x4003.9000
Offset 0x0BC
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
TSH0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3:0
Name
reserved
TSH0
Type
RO
RW
Reset
0x0
0x0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1st Sample and Hold Period Select
The TSH0 field is used during the first sample of a sequence executed
with the sample sequencer.
1140
Texas Instruments-Production Data
June 18, 2014