TM4C1292NCPDT Datasheet, PDF (532/1822 Pages) Texas Instruments – Tiva Microcontroller

Hibernation Module
7.3.5.2
7.3.5.3
If the RTC is enabled, only a cold POR, where both V_BAT and V_DD are removed, resets the RTC
registers. If any other reset occurs while the RTC is enabled, such as an external RST assertion or
BOR reset, the RTC is not reset. The RTC registers can be reset under any type of system reset
as long as the RTC, external wake pins and tamper pins are not enabled.
A buffered version of the 32.768-kHz signal Hibernate clock source is available on the RTCCLK
signal output, which is muxed with a GPIO pin. The RTCCLK signal can be the external 32.786-kHz
clock source or the HIB LFIOSC depending on the value of the OSCSEL bit in the HIBCTL register.
See “Signal Description” on page 525 or pin mux information and “General-Purpose Input/Outputs
(GPIOs)” on page 734 for additional details on initialization and configuration of this signal. The pin
does not output RTCCLK when Hibernate mode is active or before the RTCCLK GPIO digital function
has been selected through the GPIO Digital Enable (GPIODEN) register in the GPIO module. This
includes selecting the RTCCLK signal as an output source in the GPIO Port Control (GPIOPCTL)
register and setting the SYSCLKEN bit within the Hibernate Clock Control (HIBCC) register.
Note: The HIB low-frequency oscillator (HIB LFIOSC) has a wide frequency variation, therefore
the RTC is not accurate when using this clock source. In addition, the RTCCLK signal may
not meet the specification shown in Table 27-30 on page 1777.
RTC Match - Seconds/Subseconds Mode
The Hibernation module includes a 32-bit match register, HIBRTCM0, which is compared to the
value of the RTC 32-bit counter, HIBRTCC. The match functionality also extends to the sub-seconds
counter. The 15-bit field (RTCSSM) in the HIBRTCSS register is compared to the value of the 15-bit
sub-seconds counter. When a match occurs, the RTCALT0 bit is set in the HIBRIS register. For
applications using Hibernate mode, the processor can be programmed to wake from Hibernate
mode by setting the RTCWEN bit in the HIBCTL register. The processor can also be programmed to
generate an interrupt to the interrupt controller by setting the RTCALT0 bit in the HIBIM register.
The match interrupt generation takes priority over an interrupt clear. Therefore, writes to the RTCALT0
bit in the Hibernation Interrupt Clear (HIBIC) register do not clear the RTCALT0 bit if the HIBRTCC
value and the HIBRTCM0 value are equal. There are several methodologies to avoid this occurrence,
such as writing a new value to the HIBRTCLD register prior to writing the HIBIC to clear the RTCALT0.
Another example, would be to disable the RTC and re-enable the RTC by clearing and setting the
RTCEN bit in the HIBCTL register.
Note:
A Hibernate request made while a match event is valid causes the module to immediately
wake up. This occurs when the RTCWEN bit is set and the RTCALT0 bit in the HIBRIS register
is set at the same time the HIBREQ bit in the HIBCTL register is written to a 1. This can be
avoided by clearing the RTCAL0 bit in the HIBRIS register by writing a 1 to the corresponding
bit in the HIBIC register before setting the HIBREQ bit. Another example would be to disable
the RTC and re-enable the RTC by clearing and setting the RTCEN bit in the HIBCTL register.
RTC Calendar
The RTC Calendar function is selected by setting the CALEN bit in the HIB Calendar Control
(HIBCALCTL) register. In this mode, six 32-bit registers provide the read (HIBCAL0/1), match
(HIBCALM0/1), and load (HIBCALLD0/1) interface. The standard RTC registers: HIBRTCC,
HIBRTCLD, HIBRTCSS, and HIBRTCM0 are disabled when the calendar function is enabled and
read back as all 0s in this mode. In addition, writes have no effect on these registers when the
calendar function is enabled.
The Hibernation Calendar n (HIBCALn), Hibernation Calendar Match (HIBCALMn) and
Hibernation Calendar Load (HIBCALLDn) register fields are written or stored in hexadecimal.
532
June 18, 2014
Texas Instruments-Production Data