SM320C6472-HIREL Datasheet, PDF (82/264 Pages) Texas Instruments – SM320C6472 Fixed-Point Digital Signal Processor

SM320C6472-HiRel
SPRS696B – SEPTEMBER 2010 – REVISED OCTOBER 2010
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3.8.2 Reset Mux Registers (RSTMUX0-RSTMUX5)
The reset controller has inputs for each of the watchdog timer outputs. The reset mux registers determine
the method of reset that will be used when a watchdog timeout occurs.
31
Reserved
R-0000 0000 0000 0000 0000 000
15
9
Reserved
R-0000 0000 0000 0000 0000 000
7
6
5
4
3
1
DELAY
Reserved
EVTSTAT
OMODE
R/W-100
R-0
RC-0
R/W-000
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Figure 3-14. Reset Mux Registers (RSTMUX0-RSTMUX5)
16
8
DELAY
R/W-100
0
LOCK
R/W-0
Bit Field
31:9 Reserved
8:6 DELAY
5 Reserved
4 EVTSTAT
3:1 OMODE
0 LOCK
Table 3-19. Reset Mux Registers (RSTMUX0-RSTMUX5) Field Descriptions
Value Description
Reserved
000 256 CPU/6 cycles delay between NMI and local reset, when OMODE = 100.
001 512 CPU/6 cycles delay between NMI and local reset, when OMODE = 100.
010 1024 CPU/6 cycles delay between NMI and local reset, when OMODE = 100.
011 2048 CPU/6 cycles delay between NMI and local reset, when OMODE = 100.
100 4096 CPU/6 cycles delay between NMI and local reset, when OMODE = 100 (default).
101 8192 CPU/6 cycles delay between NMI and local reset, when OMODE = 100.
110 16384 CPU/6 cycles delay between NMI and local reset, when OMODE = 100.
111 32768 CPU/6 cycles delay between NMI and local reset, when OMODE = 100.
Reserved
The EVTSTAT bit indicates if any local timer event is received. The event could be a timeout event
(when the timer is configured in watchdog mode). Since there is only one output pin of a watchdog
event (WDOUT), the software can read this bit to know which one of the 6 timers has timed out.
Writing a 0 clears this bit.
0 No event received (default).
1 Timer event received by the reset mux block.
The OMODE bits determine how to handle the local timer events.
000 Timer event input to the reset mux block does not cause any output event (default).
001 Reserved
010 Timer event input to the reset mux block causes local reset input to C64x+ megamodule.
011 Timer event input to the reset mux block causes NMI input to C64x+ megamodule.
100 Timer event input to the reset mux block causes NMI input followed by local reset input to C64x+
megamodule. Delay between NMI and local reset is set in the DELAY bit field.
101 Timer event input to the reset mux block causes system reset to the PLL controller.
110 Reserved
111 Reserved
The LOCK field prevents further writes to the register when set to 1. After the software configures
the timer in watchdog mode and the appropriate routing of events to C64x+ megamodule, it is
expected to set the LOCK bit to 1. This will prevent accidental modification of the bit fields of this
register. The LOCK bit is reset to 0 only on the next reset that resets the Timer64.
0 Register fields are not locked (default).
1 Register fields are locked until the next timer reset.
82
Device Configuration
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