SM320C6472-HIREL Datasheet, PDF (219/264 Pages) Texas Instruments – SM320C6472 Fixed-Point Digital Signal Processor

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HEX ADDRESS RANGE
02C8 023C
02C8 0240
02C8 0244
02C8 0248
02C8 024C
02C8 0250
02C8 0254
02C8 0258
02C8 025C
02C8 0260
02C8 0264
02C8 0268
02C8 026C
02C8 0270
02C8 0274
02C8 0278
02C8 027C
02C8 0280
02C8 0284
02C8 0288
02C8 028C
02C8 0290 - 02C8 02FC
HEX ADDRESS RANGE
02CC 0000
02CC 0004
02CC 0008
02CC 000F
02CC 0010
02CC 0014
02CC 0018
02CC 001C
02CC 0020 - 02CC 007C
02CC 0080
02CC 0084
02CC 0088
02CC 008C
02CC 0090
02CC 0094
02CC 0098 - 02CC 009C
02CC 00A0
02CC 00A4
02CC 00A8
02CC 00AC
02CC 00B0
SM320C6472-HiRel
SPRS696B – SEPTEMBER 2010 – REVISED OCTOBER 2010
Table 7-102. EMAC0 Statistics Registers (continued)
ACRONYM
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
TXCOLLISION
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
FRAME64
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
-
REGISTER NAME
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Transmit Collision Frames Register
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
Transmit and Receive 64 Octet Frames Register
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns
Register
Reserved
Table 7-103. EMAC1 Control Registers
ACRONYM
TXIDVER
TXCONTROL
TXTEARDOWN
-
RXIDVER
RXCONTROL
RXTEARDOWN
-
-
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
MACEOIVECTOR
-
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
Transmit Teardown Register
Reserved
Receive Identification and Version Register
Receive Control Register
Receive Teardown Register
Reserved
Reserved
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
MAC End-of-Interrupt Vector Register
Reserved
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
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C64x+ Peripheral Information and Electrical Specifications 219
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