SM320C6472-HIREL Datasheet, PDF (45/264 Pages) Texas Instruments – SM320C6472 Fixed-Point Digital Signal Processor

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SIGNAL
NAME
AV_DDA3
AV_DDA4
DV_DDD
DV_DDR
DV_DD18
SM320C6472-HiRel
SPRS696B – SEPTEMBER 2010 – REVISED OCTOBER 2010
Table 2-5. Terminal Functions (continued)
TYPE⁽¹⁾ IPD/IPU^{(2) (3)}
NO.
DESCRIPTION
B21
I
1.8-V DDR PLL analog supply voltage
NC or connected to V_SS, if DDR is not used
NOTE: If the DDR2 Memory Controller is not used, the DV_DD18,
DV_DD18MON, V_REFSSTL, AV_DDA3, AV_DDA4, CV_DD1, PTV18P, and
PTV18N pins can be NC or connected directly to V_SS (GND) to
save power. However, connecting these pins this way prevents
boundary scan from functioning on the DDR2 Memory Controller
pins. To preserve boundary-scan functionality on the DDR2
Memory Controller pins, see Section 7.3.3.
H4
I
A21
1.8-V DDR analog supply voltage
NC or connected to V_SS, if DDR is not used
NOTE: If the DDR2 Memory Controller is not used, the DV_DD18,
DV_DD18MON, V_REFSSTL, AV_DDA3, AV_DDA4, CV_DD1, PTV18P, and
PTV18N pins can be NC or connected directly to V_SS (GND) to
save power. However, connecting these pins this way prevents
boundary scan from functioning on the DDR2 Memory Controller
pins. To preserve boundary-scan functionality on the DDR2
Memory Controller pins, see Section 7.3.3.
T23
I
V23
1.2-V RapidIO digital supply voltage
NC or connected to V_SS, if RapidIO is not used
Do not connect this SERDES supply to CV_DD1
NOTE: If the RapidIO interface is not used, the CV_DD2, AV_DDA,
DV_DDD, DV_DDR, and AV_DDT pins can be NC or connected directly
to V_SS (GND) to reduce power use. However, connecting these
pins in this way prevents boundary scan from functioning on the
RapidIO pins. To preserve boundary-scan functionality on the
RapidIO pins, see Section 7.3.3.
R28
I
1.5-V/1.8-V RapidIO regulator supply voltage
NC or connected to V_SS, if RapidIO is not used
NOTE: If the RapidIO interface is not used, the CV_DD2, AV_DDA,
DV_DDD, DV_DDR, and AV_DDT pins can be NC or connected directly
to V_SS (GND) to reduce power use. However, connecting these
pins in this way prevents boundary scan from functioning on the
RapidIO pins. To preserve boundary-scan functionality on the
RapidIO pins, see Section 7.3.3.
A1
A19
B10
B14
B5
E1
E12
E16
E6
F15
F17
I
F19
G10
G12
1.8-V I/O supply voltage for DDR2 buffers
NC or connected to V_SS, if DDR is not used
NOTE: If the DDR2 Memory Controller is not used, the DV_DD18,
DV_DD18MON, V_REFSSTL, AV_DDA3, AV_DDA4, CV_DD1, PTV18P, and
PTV18N pins can be NC or connected directly to V_SS (GND) to
save power. However, connecting these pins this way prevents
boundary scan from functioning on the DDR2 Memory Controller
pins. To preserve boundary-scan functionality on the DDR2
Memory Controller pins, see Section 7.3.3.
G14
G16
G18
G6
G8
H7
J6
Copyright © 2010, Texas Instruments Incorporated
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