SM320C6472-HIREL Datasheet, PDF (162/264 Pages) Texas Instruments – SM320C6472 Fixed-Point Digital Signal Processor

SM320C6472-HiRel
SPRS696B – SEPTEMBER 2010 – REVISED OCTOBER 2010
www.ti.com
7.9.3.2 PLL2 PLL Control Register (PLLCTL)
The PLL control register (PLLCTL) is shown in Figure 7-27 and described in Table 7-35.
31
16
Reserved
R-00 0001h
15
8
Reserved
R-00 0001h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
7
6
Rsvd
Rsvd
R/W-0 R-1
5
4
Reserved
R/W-10
3
PLLRST
R/W-1
2
Rsvd
R-0
1
PLL
PWRDN
R/W-0
0
PLLEN
R/W-0
Figure 7-27. PLL Control Register (PLLCTL)
Table 7-35. PLL Control Register (PLLCTL) Field Descriptions⁽¹⁾
Bit Field
31:8 Reserved
7 Reserved
6 Reserved
5:4 Reserved
3 PLLRST
2 Reserved
1 PLLPWRDN
0 PLLEN
Value
0
1
0
1
0
1
Description
Reserved. The reserved bit location is always read as 00 0001h. A value written to this field has no
effect.
Reserved. Writes to this register must keep this bit as 0.
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
Reserved. Writes to this register must always program these bits as 00.
PLL reset bit
PLL reset is released
PLL reset is asserted
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLL power-down mode select bit
PLL is operational
PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off
PLL enable bit
Bypass mode. PLL is bypassed. All the system clocks (SYSCLKn) are divided down directly from
input reference clock.
PLL mode. PLL is not bypassed. PLL output path is enabled. All the system clocks (SYSCLKn) are
divided down from PLL output.
(1) The value of this register is changed by the ROM bootloader.
162 C64x+ Peripheral Information and Electrical Specifications
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s) :SM320C6472-HiRel