TLK3101_16 Datasheet, PDF (8/28 Pages) Texas Instruments – 2.5 Gbps to 3.125 Gbps TRANSCEIVER

TLK3101
2.5 Gbps to 3.125 Gbps TRANSCEIVER
SCAS649B − AUGUST 2000 − REVISED JANUARY 2008
receive interface (continued)
common detect and 8-b/10-b decoding
The TLK3101 has two parallel 8-b/10-b decode circuits. Each 8-b/10-b decoder converts 10 bit encoded data
(half of the 20 bit received word) back into 8 bits. The comma detect circuit is designed to provide for byte
synchronization to an 8-b/10-b transmission code. When parallel data is clocked into a parallel to serial
converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data.
When the serial data is received and converted to parallel format again a way is needed to be able to recognize
the byte boundary again. Generally this is accomplished through the use of a synchronization pattern. This is
generally a unique pattern of 1s and 0s that either cannot occur as part of valid data or is a pattern that repeats
at defined intervals. 8-bit/10-bit encoding contains a character called the comma (b’0011111’ or b’1100000’)
which is used by the comma detect circuit on the TLK3101 to align the received serial data back to its original
byte boundary. The decoder detects the K28.5 comma, generating a synchronization signal aligning the data
to their 10 bit boundaries for decoding. It then converts the data back into 8 bit data, removing the control words.
The output from the two decoders is latched into the 16 bit register synchronized to the recovered parallel data
clock (RX_CLK) and the output is valid on the rising edge of RX_CLK.
It is possible for a single bit error in a data packet to be misinterpreted as a comma on an erroneous boundary.
If the erroneous comma were taken as the new byte boundary, all subsequent data would be erroneously
decoded until a properly aligned comma was detected. To prevent a data bit error in a data packet from being
interpreted as a comma, the comma word alignment circuit is turned off after receiving a properly aligned comma
after the link is properly established. The link is established after three idle patterns or one valid data pattern
is properly received. The comma alignment circuit is re-enabled when the synchronization state machine
detects a loss of synchronization condition (see synchronization and initialization).
Two output signals, RX_DV/LOS and RX_ER, are generated along with the decoded 16-bit data output on the
RXD[0:15] pins. The output status signals are asserted according to Table 3. When the TLK3101 decodes
normal data and outputs the data on RXD[0:15], RX_DV/LOS is asserted (logic high) and RX_ER is deasserted
(logic low). When the TLK3101 decodes a K23.7 code (F7F7) indicating carrier extend, RX_DV/LOS is
deasserted and RX_ER is asserted. If the decoded data is not a valid 8-b/10-b code, an error is reported by the
assertion of both RX_DV/LOS and RX_ER. If the error was due to an error propagation code, the RXD[15:0]
pins will output hex FEFE. If the error was due to an invalid pattern, the data output on RXD is undefined. When
the TLK3101 decodes an IDLE code, both RX_DV/LOS and RX_ER are deasserted and a K28.5 (BC) code is
output on the RXD[7:0] pins and either a D5.6 (C5) or D16.2 (50) code is output on the RXD[15:8] pins.
Table 3. Receive Status Signals
RECEIVED 20 BIT DATA
IDLE (<K28.5, D5.6>, <K28.5, D16.2>)
Carrier extend (K23.7, K23.7)
Normal data character (DX.Y)
Receive error propagation (K30.7, K30.7)
RX_DV/LOS
0
0
1
1
RX_ER
0
1
0
1
loss of signal detection
The TLK3101 has a loss of signal detection circuit for conditions where the incoming signal no longer has a
sufficient voltage level to keep the clock recovery circuit in lock. The signal detection circuit is intended to be
an indication of gross signal error conditions such as a detached cable or no signal being transmitted, and not
an indication of signal coding health. The TLK3101 reports this condition by asserting, RX_DV/LOS, RX_ER
and RXD[0:15] all to a high state. As long as the signal is above 200 mV in differential magnitude, the LOS circuit
will not signal an error condition.
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