TLK3101_16 Datasheet, PDF (10/28 Pages) Texas Instruments – 2.5 Gbps to 3.125 Gbps TRANSCEIVER

TLK3101
2.5 Gbps to 3.125 Gbps TRANSCEIVER
SCAS649B − AUGUST 2000 − REVISED JANUARY 2008
synchronization and initialization (continued)
The state of the transmit data bus, control pins, and serial outputs during the link acquisition process is illustrated
in Figure 7.
ACQ
SYNC
TX_EN ^{xx xx xx xx xx xx xx}
TX_ER xx xx xx xx xx xx xx
TXD(0−15) xx xx xx xx xx xx xx xx
D0−D15
DOUTTXP,
DOUTTXN
IDLE
D0−D15
Ca. Ext.
Error
Figure 7. Transmit Side Timing Diagram
The state of the receive data bus, status pins, and serial inputs during the link acquisition process is illustrated
in Figure 8 and Figure 9.
ACQ
SYNC
DINRXP,
DINRXN
IDLE or Carrier
Extend
IDLE or Carrier
Extend
IDLE or Carrier
Extend
D0−D15
RXD(0−15)
RX_DV,
RX_ER
XXXXXXXXXXXXXXXXXXX
IDLE or Carrier
Extend
IDLE or Carrier
Extend
D0−D15
RESET
(Internal Signal)
Figure 8. Receive Side Timing Diagram (IDLE or Carrier Extend)
ACQ
SYNC
DINRXP,
DINRXN
IDLE
Valid Data or
Error Prop
D0−D15
D0−D15
RXD(0−15)
RX_DV,
RX_ER
XXXXXXXXXXXXXXXXXXX
Valid Data or
ÉÉÉÉÉÉÉÉ ^{Error Prop}
D0−D15
D0−D15
RESET
(Internal Signal)
Figure 9. Receive Side Timing Diagram (Valid Data or Error Propagation)
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